Hazard3/test/sim/debug_openocd_bitbang
Luke Wren 307955c810 Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference 2021-07-13 01:10:55 +01:00
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.gitignore Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
Makefile Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
openocd.cfg Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
tb.cpp Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference 2021-07-13 01:10:55 +01:00
tb.f Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
tb.v Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
waves.gtkw Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00