105 lines
2.3 KiB
Verilog
105 lines
2.3 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// FPGA toplevel for ../soc/example_soc.v on an iCEBreaker dev board
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`default_nettype none
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module fpga_icebreaker (
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input wire clk_osc,
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// No external trst_n as iCEBreaker can't easily drive it from FTDI, so we
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// generate a pulse internally from FPGA PoR.
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input wire tck,
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input wire tms,
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input wire tdi,
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output wire tdo,
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output wire led,
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output wire mirror_tck,
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output wire mirror_tms,
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output wire mirror_tdi,
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output wire mirror_tdo,
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output wire uart_tx,
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input wire uart_rx
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);
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assign mirror_tck = tck;
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assign mirror_tms = tms;
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assign mirror_tdi = tdi;
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assign mirror_tdo = tdo;
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wire clk_sys = clk_osc;
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wire rst_n_sys;
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wire trst_n;
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fpga_reset #(
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.SHIFT (3)
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) rstgen (
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.clk (clk_sys),
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.force_rst_n (1'b1),
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.rst_n (rst_n_sys)
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);
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reset_sync trst_sync_u (
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.clk (tck),
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.rst_n_in (rst_n_sys),
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.rst_n_out (trst_n)
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);
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activity_led #(
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.WIDTH (1 << 8),
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.ACTIVE_LEVEL (1'b0)
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) tck_led_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.i (tck),
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.o (led)
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);
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example_soc #(
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.CLK_MHZ (12),
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.EXTENSION_A (1),
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.EXTENSION_C (0),
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.EXTENSION_M (1),
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.EXTENSION_ZBA (0),
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.EXTENSION_ZBB (0),
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.EXTENSION_ZBC (0),
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.EXTENSION_ZBS (0),
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.EXTENSION_ZBKB (0),
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.EXTENSION_ZIFENCEI (0),
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.EXTENSION_XH3BEXTM (0),
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.EXTENSION_XH3PMPM (0),
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.EXTENSION_XH3POWER (0),
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.CSR_COUNTER (0),
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.U_MODE (0),
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.PMP_REGIONS (0),
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.BREAKPOINT_TRIGGERS (0),
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.IRQ_PRIORITY_BITS (0),
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.REDUCED_BYPASS (0),
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.MULDIV_UNROLL (1),
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.MUL_FAST (0),
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.MUL_FASTER (0),
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.MULH_FAST (0),
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.FAST_BRANCHCMP (1),
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.BRANCH_PREDICTOR (0)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.tck (tck),
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.trst_n (trst_n),
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.tms (tms),
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.tdi (tdi),
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.tdo (tdo),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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);
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endmodule
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