99 lines
2.1 KiB
Verilog
99 lines
2.1 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module fpga_orangecrab_25f (
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input wire clk_osc,
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output wire [7:0] dbg,
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output wire uart_tx,
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input wire uart_rx,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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output rst_n,
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input usr_btn
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);
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wire clk_sys = clk_osc;
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wire rst_n_sys;
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wire trst_n;
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fpga_reset #(
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.SHIFT (3)
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) rstgen (
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.clk (clk_sys),
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.force_rst_n (1'b1),
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.rst_n (rst_n_sys)
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);
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example_soc #(
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.DTM_TYPE ("ECP5"),
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.SRAM_DEPTH (1 << 14),
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.CLK_MHZ (48),
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.EXTENSION_M (1),
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.EXTENSION_A (1),
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.EXTENSION_C (0),
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.EXTENSION_ZBA (0),
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.EXTENSION_ZBB (0),
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.EXTENSION_ZBC (0),
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.EXTENSION_ZBS (0),
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.EXTENSION_ZBKB (0),
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.EXTENSION_ZIFENCEI (1),
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.EXTENSION_XH3BEXTM (0),
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.EXTENSION_XH3PMPM (0),
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.EXTENSION_XH3POWER (0),
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.CSR_COUNTER (1),
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.MUL_FAST (1),
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.MUL_FASTER (0),
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.MULH_FAST (0),
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.MULDIV_UNROLL (1),
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.FAST_BRANCHCMP (1),
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.BRANCH_PREDICTOR (1)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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// JTAG connections provided internally by ECP5 JTAGG primitive
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.tck (1'b0),
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.trst_n (1'b0),
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.tms (1'b0),
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.tdi (1'b0),
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.tdo (/* unused */),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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);
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// Create a 27 bit register
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reg [26:0] counter = 0;
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// Every positive edge increment register by 1
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always @(posedge clk_sys) begin
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counter <= counter + 1;
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end
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// Output inverted values of counter onto LEDs
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assign rgb_led0_r = ~counter[24];
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assign rgb_led0_g = ~counter[25];
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assign rgb_led0_b = 0;
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assign dbg = 8'hff;
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// Reset logic on button press.
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// this will enter the bootloader
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reg reset_sr = 1'b1;
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always @(posedge clk_sys) begin
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reset_sr <= {usr_btn};
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end
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assign rst_n = reset_sr;
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endmodule
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