Luke Wren c550d79047 Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions		2024-05-12 13:33:14 +01:00
..
riscv-tests@7d3eefd6b3	Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions	2024-05-12 13:33:14 +01:00
debug.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
run-debug-tests.sh	Fix up HwbpManual test in riscv-tests fork, and update debug test list	2023-03-24 00:28:02 +00:00
run-isa-tests.sh	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh	Capture JTAG bitbang log from most recent SMP debug test.	2023-03-31 02:16:23 +01:00