Hazard3

History

Luke Wren 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.		2021-12-07 19:24:53 +00:00
..
diagrams	Finish documenting CSRs. Draw a debug topology diagram.	2021-11-28 08:17:23 +00:00
sections	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.	2021-12-07 19:24:53 +00:00
Makefile	Document some IRQ CSRs, and instruction timings	2021-05-31 15:57:05 +01:00
Readme.md	Document some IRQ CSRs, and instruction timings	2021-05-31 15:57:05 +01:00
hazard3.adoc	Finish documenting CSRs. Draw a debug topology diagram.	2021-11-28 08:17:23 +00:00
hazard3.pdf	Add A bit to MISA, update docs	2021-12-07 05:10:20 +00:00

Building

# Get tools
sudo apt install ruby-asciidoctor-pdf
# Build
make