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Hazard3/hdl
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Luke Wren 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. 
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
 		2021-12-07 19:24:53 +00:00
..
arith Don't apply shifter assertions to rotates 2021-12-06 18:12:23 +00:00
debug Remove UART DTM 2021-12-02 02:08:16 +00:00
peri Add default_nettype none at top of every file, and default_nettype wire at bottom 2021-11-23 22:10:39 +00:00
hazard3.f Sketch in AMO support 2021-12-04 20:46:39 +00:00
hazard3_config.vh Add basic support for lr/sc instructions from the A extension 2021-12-04 15:02:31 +00:00
hazard3_config_inst.vh Add basic support for lr/sc instructions from the A extension 2021-12-04 15:02:31 +00:00
hazard3_core.v Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend 2021-12-06 19:28:21 +00:00
hazard3_cpu_1port.v Add basic support for lr/sc instructions from the A extension 2021-12-04 15:02:31 +00:00
hazard3_cpu_2port.v Add basic support for lr/sc instructions from the A extension 2021-12-04 15:02:31 +00:00
hazard3_csr.v Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. 2021-12-07 19:24:53 +00:00
hazard3_decode.v Fix atomic instructions not asserting decode error when A extension is disabled 2021-12-06 07:28:50 +00:00
hazard3_frontend.v Cleanup order of declaration/use of a couple of wires 2021-11-25 15:16:59 +00:00
hazard3_instr_decompress.v Add default_nettype none at top of every file, and default_nettype wire at bottom 2021-11-23 22:10:39 +00:00
hazard3_ops.vh Add RISC-V opcodes and memory operation codes for atomics 2021-12-04 11:16:24 +00:00
hazard3_regfile_1w2r.v Add default_nettype none at top of every file, and default_nettype wire at bottom 2021-11-23 22:10:39 +00:00
hazard3_width_const.vh Add RISC-V opcodes and memory operation codes for atomics 2021-12-04 11:16:24 +00:00
rv_opcodes.vh Add RISC-V opcodes and memory operation codes for atomics 2021-12-04 11:16:24 +00:00