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Hazard3/test/sim/riscv-compliance
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Luke Wren 3c61fae9ef Remove the halfword fetch thing, was only really useful on RISCBoy 2022-04-02 10:54:16 +01:00
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include Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
riscv-arch-test@b436dd0939 Fix remaining fallout from tb args change 2021-12-11 09:53:39 +00:00
.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
compare_testvec Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
memmap.ld Remove padding after vector table in init.S 2021-12-11 12:22:23 +00:00
run_32i.sh Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings. 2021-12-18 00:35:13 +00:00
run_32ic.sh Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings. 2021-12-18 00:35:13 +00:00
run_32im.sh Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings. 2021-12-18 00:35:13 +00:00
run_32privilege.sh Add run_all script under riscv-compliance 2021-12-11 12:08:53 +00:00
run_all.sh Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings. 2021-12-18 00:35:13 +00:00
test.gtkw Remove the halfword fetch thing, was only really useful on RISCBoy 2022-04-02 10:54:16 +01:00