Hazard3/test/sim/tb_cxxrtl/Makefile

32 lines
1.0 KiB
Makefile

# To build single-core dual-port tb: make
# To build dual-core single-port tb: make DOTF=tb_multicore.f
TOP := tb
DOTF := tb.f
CONFIG := default
TBEXEC := $(patsubst %.f,%,$(DOTF))
# Note: clang++-18 has a >20x compile time regression, even at low
# optimisation levels. I have tried clang++-16 and clang++-17, both fine.
CLANGXX := clang++-16
.PHONY: clean all
all: $(TBEXEC)
SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(shell listfiles $(DOTF));
SYNTH_CMD += hierarchy -top $(TOP);
SYNTH_CMD += write_cxxrtl build-$(DOTF)/dut.cpp
CDEFINES_tb_multicore.f := WIDE_TIMER_IRQ
build-$(DOTF)/dut.cpp: $(shell listfiles $(DOTF)) $(wildcard *.vh)
mkdir -p build-$(DOTF)
yosys -p '$(SYNTH_CMD)' 2>&1 > build-$(DOTF)/cxxrtl.log
clean::
rm -rf build-$(DOTF) $(TBEXEC)
$(TBEXEC): build-$(DOTF)/dut.cpp tb.cpp
$(CLANGXX) -O3 -std=c++14 $(addprefix -D,$(CDEFINES) $(CDEFINES_$(DOTF))) -I $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime -I build-$(DOTF) tb.cpp -o $(TBEXEC)