Luke Wren 5d2a562f65 Just use read_verilog; write_cxxrtl when building tb_cxxrtl		2021-07-22 17:30:30 +01:00
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.gitignore	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
Makefile	Just use read_verilog; write_cxxrtl when building tb_cxxrtl	2021-07-22 17:30:30 +01:00
tb.cpp	Double-step() after clock posedge to workaround CXXRTL port propagation issue	2021-07-18 16:03:53 +01:00