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arith
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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Makefile
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3.f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_config.vh
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_config_inst.vh
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_core.v
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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hazard3_cpu_1port.v
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_cpu_2port.v
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_csr.v
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_decode.v
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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hazard3_frontend.v
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Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
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2021-05-22 10:16:02 +01:00 |
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hazard3_instr_decompress.v
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_ops.vh
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_regfile_1w2r.v
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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hazard3_rvfi_monitor.vh
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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
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2021-05-23 06:40:44 +01:00 |
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hazard3_rvfi_wrapper.v
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Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
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2021-05-22 15:35:52 +01:00 |
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hazard3_width_const.vh
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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rv_opcodes.vh
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Import from hazard5 9743a1b
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2021-05-21 02:34:16 +01:00 |
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