Luke Wren 65bfca5fdf Fix latent bug with asynchronous debug entry during stalled load/store address phase		2021-09-04 07:49:29 +01:00
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arith	Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends	2021-07-20 00:13:26 +01:00
debug	Small code cleanup	2021-07-24 10:08:27 +01:00
peri	Clean up timer	2021-08-21 17:03:32 +01:00
hazard3.f	More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus	2021-05-29 18:00:43 +01:00
hazard3_config.vh	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_config_inst.vh	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_core.v	Add instruction fetch faults	2021-09-04 02:57:39 +01:00
hazard3_cpu_1port.v	Add instruction fetch faults	2021-09-04 02:57:39 +01:00
hazard3_cpu_2port.v	Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry	2021-07-17 19:26:45 +01:00
hazard3_csr.v	Fix latent bug with asynchronous debug entry during stalled load/store address phase	2021-09-04 07:49:29 +01:00
hazard3_decode.v	Add instruction fetch faults	2021-09-04 02:57:39 +01:00
hazard3_frontend.v	Add instruction fetch faults	2021-09-04 02:57:39 +01:00
hazard3_instr_decompress.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_ops.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
hazard3_regfile_1w2r.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_width_const.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
rv_opcodes.vh	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00