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Hazard3/test/sim/tb_cxxrtl
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Luke Wren 9e2f5df00a Add testbench flag to propagate CPU return code to testbench return 2022-05-28 15:00:28 +01:00
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.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Build tb with 4 PMP regions by default 2022-05-24 20:06:57 +01:00
compliance.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
gdbinit Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
multicore-openocd.cfg Add multicore tb integration file 2021-12-17 00:41:23 +00:00
multicore.gtkw tb: handle both ports identically. Preparing for dual core 2021-12-17 00:04:00 +00:00
openocd.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb.cpp Add testbench flag to propagate CPU return code to testbench return 2022-05-28 15:00:28 +01:00
tb.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb.v Add minimal multicore launch code 2021-12-17 01:24:11 +00:00
tb_common.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb_multicore.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb_multicore.v Add minimal multicore launch code 2021-12-17 01:24:11 +00:00
waves.gtkw Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00