Hazard3/example_soc
Scott Shawcroft 4c12f163bd
Add OrangeCrab 25F support (#7)
* Add OrangeCrab 25F support

* Fix whitespace

Co-authored-by: Luke Wren <wren6991@gmail.com>
2022-12-17 11:49:41 +00:00
..
fpga Add OrangeCrab 25F support (#7) 2022-12-17 11:49:41 +00:00
libfpga@9d50e12e01 Bump libfpga for correct bus error response from AHBL splitter in example SoC 2021-11-28 01:35:52 +00:00
soc Add RISC-V timer to example soc, and tweak ULX3S config 2022-10-07 03:11:36 +01:00
synth Add OrangeCrab 25F support (#7) 2022-12-17 11:49:41 +00:00
icebreaker-openocd.cfg Small code cleanup 2021-07-24 10:08:27 +01:00
ulx3s-openocd.cfg Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG. 2021-07-23 18:32:47 +01:00