Luke Wren 799f4f2c26 Fix verilator lint width issues in triggers, PMP, DM. ... There was one genuine issue introduced by PPA changes in 78a5cb98e which affected instruction injection on multiple harts from the DM (indicating SMP debug testing needs to be part of regular automated regressions, instead of semi-manual...). The rest are cosmetic.		2024-05-29 15:32:45 +01:00
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arith	Fix a few width issues identified by verilator lint. All of them gave	2024-05-26 17:32:24 +01:00
debug	Fix verilator lint width issues in triggers, PMP, DM.	2024-05-29 15:32:45 +01:00
hazard3.f	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_config.vh	Avoid zero-total-width concatenations for parameters parameterised	2024-05-26 16:47:20 +01:00
hazard3_config_inst.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
hazard3_core.v	Fix a few width issues identified by verilator lint. All of them gave	2024-05-26 17:32:24 +01:00
hazard3_cpu_1port.v	Fix use of non-always-on clock for arbitration of load/store vs SBA,	2024-03-17 05:46:01 +00:00
hazard3_cpu_2port.v	Fix use of non-always-on clock for arbitration of load/store vs SBA,	2024-03-17 05:46:01 +00:00
hazard3_csr.v	Set misa.b when all of Zba, Zbb and Zbs are enabled.	2024-05-11 12:13:35 +01:00
hazard3_csr_addr.vh	First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.	2022-08-22 08:47:03 +01:00
hazard3_decode.v	Remove conditioning of uop_atomic flag on non-invalid instructions,	2024-05-29 15:32:38 +01:00
hazard3_frontend.v	Fix a few width issues identified by verilator lint. All of them gave	2024-05-26 17:32:24 +01:00
hazard3_instr_decompress.v	PPA: simplify generation of uop_atomic and uop_seq_end flags in instr_decompress to be independent of most instruction bits. Add some new assertions on behaviour of uop signals outside of uop sequences.	2024-05-26 16:24:07 +01:00
hazard3_irq_ctrl.v	Tidy up priority tie-offs in irq_ctrl	2022-10-08 16:25:05 +01:00
hazard3_ops.vh	Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains	2022-08-06 23:02:08 +01:00
hazard3_pmp.v	Fix verilator lint width issues in triggers, PMP, DM.	2024-05-29 15:32:45 +01:00
hazard3_power_ctrl.v	Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.	2022-11-05 18:26:56 +00:00
hazard3_regfile_1w2r.v	Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression	2022-09-04 23:56:14 +01:00
hazard3_triggers.v	Fix verilator lint width issues in triggers, PMP, DM.	2024-05-29 15:32:45 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00