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arith
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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debug
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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peri
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3.f
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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hazard3_config.vh
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First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
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2022-05-24 16:17:54 +01:00 |
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hazard3_config_inst.vh
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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hazard3_core.v
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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hazard3_cpu_1port.v
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Wire privilege through from core to bus masters. Tied off inside core.
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2022-05-24 14:05:26 +01:00 |
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hazard3_cpu_2port.v
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Wire privilege through from core to bus masters. Tied off inside core.
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2022-05-24 14:05:26 +01:00 |
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hazard3_csr.v
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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hazard3_csr_addr.vh
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First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
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2022-05-24 16:17:54 +01:00 |
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hazard3_decode.v
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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hazard3_frontend.v
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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hazard3_instr_decompress.v
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_ops.vh
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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hazard3_pmp.v
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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hazard3_regfile_1w2r.v
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Remove unused FAKE_DUALPORT option from regfile
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2022-05-23 16:22:01 +01:00 |
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hazard3_width_const.vh
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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rv_opcodes.vh
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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