colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Hazard3/test/sim
History
Luke Wren c56c75e14b More dicking with yosys cmd for tb_cxxrtl; 
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
 		2021-07-18 16:46:00 +01:00
..
common Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why. 2021-06-04 09:19:18 +01:00
coremark Update init.S for new IRQ functionality 2021-06-04 08:16:54 +01:00
debug_module_vectors Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference 2021-07-13 01:10:55 +01:00
dhrystone Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
ecall_simple Update init.S for new IRQ functionality 2021-06-04 08:16:54 +01:00
hellow Update init.S for new IRQ functionality 2021-06-04 08:16:54 +01:00
openocd Double-step() after clock posedge to workaround CXXRTL port propagation issue 2021-07-18 16:03:53 +01:00
riscv-compliance Add 32IM testlist 2021-06-05 12:03:05 +01:00
rvcpp Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
rvpy Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
tb_cxxrtl More dicking with yosys cmd for tb_cxxrtl; 2021-07-18 16:46:00 +01:00