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Hazard3/hdl
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Luke Wren e16ae06cb5 Clean up timer 2021-08-21 17:03:32 +01:00
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arith Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends 2021-07-20 00:13:26 +01:00
debug Small code cleanup 2021-07-24 10:08:27 +01:00
peri Clean up timer 2021-08-21 17:03:32 +01:00
hazard3.f More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_config.vh Start hacking in debug support to the core -- seems to work as well as before adding debug! 2021-07-10 18:53:48 +01:00
hazard3_config_inst.vh Start hacking in debug support to the core -- seems to work as well as before adding debug! 2021-07-10 18:53:48 +01:00
hazard3_core.v Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions 2021-07-16 20:43:24 +01:00
hazard3_cpu_1port.v Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry 2021-07-17 19:26:45 +01:00
hazard3_cpu_2port.v Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry 2021-07-17 19:26:45 +01:00
hazard3_csr.v Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception 2021-07-24 15:31:33 +01:00
hazard3_decode.v Start hacking in debug support to the core -- seems to work as well as before adding debug! 2021-07-10 18:53:48 +01:00
hazard3_frontend.v Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode 2021-07-10 21:02:18 +01:00
hazard3_instr_decompress.v Some cleanup; correctly decode 16-bit EBREAK 2021-06-03 20:03:43 +01:00
hazard3_ops.vh Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 2021-05-23 11:59:46 +01:00
hazard3_regfile_1w2r.v Some cleanup; correctly decode 16-bit EBREAK 2021-06-03 20:03:43 +01:00
hazard3_width_const.vh Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 2021-05-23 11:59:46 +01:00
rv_opcodes.vh Import from hazard5 9743a1b 2021-05-21 02:34:16 +01:00