Luke Wren 9460b3cd04 Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.		2021-12-11 15:52:34 +00:00
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arith	Don't apply shifter assertions to rotates	2021-12-06 18:12:23 +00:00
debug	Remove UART DTM	2021-12-02 02:08:16 +00:00
peri	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3.f	Sketch in AMO support	2021-12-04 20:46:39 +00:00
hazard3_config.vh	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_config_inst.vh	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_core.v	Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.	2021-12-11 15:52:34 +00:00
hazard3_cpu_1port.v	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_cpu_2port.v	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_csr.v	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.	2021-12-07 19:24:53 +00:00
hazard3_decode.v	Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic	2021-12-09 06:26:31 +00:00
hazard3_frontend.v	Fix commented out frontend properties which relied on non-constant past reset values	2021-12-07 20:24:29 +00:00
hazard3_instr_decompress.v	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3_ops.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00
hazard3_regfile_1w2r.v	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3_width_const.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00
rv_opcodes.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00