Hazard3/hdl
Luke Wren 96a9ee18e1 Add IALIGN exception to non-RVC implementations 2022-05-23 12:47:48 +01:00
..
arith Correct the name and operation of the brev8 (formerly rev.b) instruction 2022-05-20 15:28:18 +01:00
debug New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
peri New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
hazard3.f Perf option for dedicated branch comparator 2022-04-02 11:40:47 +01:00
hazard3_config.vh Implement Zbkb (untested) 2022-05-06 17:36:25 +01:00
hazard3_config_inst.vh Implement Zbkb (untested) 2022-05-06 17:36:25 +01:00
hazard3_core.v Add IALIGN exception to non-RVC implementations 2022-05-23 12:47:48 +01:00
hazard3_cpu_1port.v Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus. 2021-12-18 15:41:05 +00:00
hazard3_cpu_2port.v New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
hazard3_csr.v Don't store bit 1 of mepc on non-RVC implementations 2022-05-23 12:27:07 +01:00
hazard3_decode.v Correct the name and operation of the brev8 (formerly rev.b) instruction 2022-05-20 15:28:18 +01:00
hazard3_frontend.v Stronger property for correct predecode 2022-04-05 08:18:00 +01:00
hazard3_instr_decompress.v New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
hazard3_ops.vh Correct the name and operation of the brev8 (formerly rev.b) instruction 2022-05-20 15:28:18 +01:00
hazard3_regfile_1w2r.v Fix forward reference to net 2022-01-18 23:02:39 +00:00
hazard3_width_const.vh New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
rv_opcodes.vh Correct the name and operation of the brev8 (formerly rev.b) instruction 2022-05-20 15:28:18 +01:00