Luke Wren 47ce2cc8ec Add embench submodule, with configs for hazard3		2021-11-28 00:01:18 +00:00
..
bitmanip-random	Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation	2021-11-27 17:19:41 +00:00
common	Fix alignment of heap_ptr in init.S. Small ALU cleanup	2021-11-26 02:59:50 +00:00
coremark	Update init.S for new IRQ functionality	2021-06-04 08:16:54 +01:00
debug_module_vectors	Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference	2021-07-13 01:10:55 +01:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
ecall_simple	Update init.S for new IRQ functionality	2021-06-04 08:16:54 +01:00
embench	Add embench submodule, with configs for hazard3	2021-11-28 00:01:18 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
openocd	Fix IO decode in openocd/tb.cpp	2021-11-23 22:12:51 +00:00
riscv-compliance	Add 32IM testlist	2021-06-05 12:03:05 +01:00
riscv-tests	Update riscv-tests fork for crash loop debug test	2021-11-23 21:58:39 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
tb_cxxrtl	Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench	2021-11-06 09:59:27 +00:00
wfi_loop	Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench	2021-11-06 09:59:27 +00:00