Hazard3/hdl
Luke Wren 96e0e66597 Fix fence.i being marked invalid in debug mode.
This was done because the implementation depends on the value of PC
(it's a jump-to-next), and PC-dependent instructions are permitted to
be flagged as invalid in debug mode, to permit sharing of PC and the
dpc CSR.

However this is not valid in this case because the dependency on PC is
an implementation detail, not an architected dependency. Instead just
suppress the jump in debug mode. Suppressing the jump is still required
to avoid flushing following program buffer entries from the prefetch
queue during debug mode execution.

From a functional point of view not much has changed, it just removes
an inconsistency where fence.i appeared to be implemented in M/U mode
but not in debug mode. This removes a complaint from openocd when it
executes a fence + fence.i after writing to memory.
2024-06-01 15:38:33 +01:00
..
arith Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic. 2024-05-29 15:52:53 +01:00
debug Fix final two width lints in JTAG DTM. They now shrink the design by 100 LUTs instead of growing it? A mystery 2024-05-29 15:58:45 +01:00
hazard3.f Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module. 2022-10-05 23:53:04 +01:00
hazard3_config.vh Avoid zero-total-width concatenations for parameters parameterised 2024-05-26 16:47:20 +01:00
hazard3_config_inst.vh First attempt at Zcmp 2023-03-20 00:19:23 +00:00
hazard3_core.v Fix a few width issues identified by verilator lint. All of them gave 2024-05-26 17:32:24 +01:00
hazard3_cpu_1port.v Fix use of non-always-on clock for arbitration of load/store vs SBA, 2024-03-17 05:46:01 +00:00
hazard3_cpu_2port.v Fix use of non-always-on clock for arbitration of load/store vs SBA, 2024-03-17 05:46:01 +00:00
hazard3_csr.v Set misa.b when all of Zba, Zbb and Zbs are enabled. 2024-05-11 12:13:35 +01:00
hazard3_csr_addr.vh First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested. 2022-08-22 08:47:03 +01:00
hazard3_decode.v Fix fence.i being marked invalid in debug mode. 2024-06-01 15:38:33 +01:00
hazard3_frontend.v Fix a few width issues identified by verilator lint. All of them gave 2024-05-26 17:32:24 +01:00
hazard3_instr_decompress.v Fix event loops reported by Verilator UNOPTFLAT lints. 2024-06-01 15:25:16 +01:00
hazard3_irq_ctrl.v Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic. 2024-05-29 15:52:53 +01:00
hazard3_ops.vh Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains 2022-08-06 23:02:08 +01:00
hazard3_pmp.v Fix verilator lint width issues in triggers, PMP, DM. 2024-05-29 15:32:45 +01:00
hazard3_power_ctrl.v Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep. 2022-11-05 18:26:56 +00:00
hazard3_regfile_1w2r.v Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression 2022-09-04 23:56:14 +01:00
hazard3_triggers.v Fix verilator lint width issues in triggers, PMP, DM. 2024-05-29 15:32:45 +01:00
hazard3_width_const.vh Update copyright years 2022-06-09 00:12:01 +01:00
rv_opcodes.vh First attempt at Zcmp 2023-03-20 00:19:23 +00:00