Hazard3/test/sim/tb_cxxrtl
Luke Wren 42c4ac305b Fix deprecation warning for tb openocd.cfg, and update example output in Readme.md 2024-08-07 16:44:43 -07:00
..
.gitignore tb_cxxrtl Makefile: better support for building multiple tb configurations 2023-03-24 18:44:37 +00:00
Makefile Do not rely on environment variables for any intra-project paths 2024-05-27 16:53:06 +01:00
compliance.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
config_default.vh First attempt at Zcmp 2023-03-20 00:19:23 +00:00
config_min.vh First attempt at Zcmp 2023-03-20 00:19:23 +00:00
gdbinit Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
multicore-openocd.cfg Add multicore tb integration file 2021-12-17 00:41:23 +00:00
multicore.gtkw Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench) 2022-07-06 23:53:11 +01:00
openocd.cfg Fix deprecation warning for tb openocd.cfg, and update example output in Readme.md 2024-08-07 16:44:43 -07:00
tb.cpp tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about. 2024-05-27 12:24:54 +01:00
tb.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb.v tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about. 2024-05-27 12:24:54 +01:00
tb_common.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb_multicore.f Add multicore tb integration file 2021-12-17 00:41:23 +00:00
tb_multicore.v tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about. 2024-05-27 12:24:54 +01:00
waves.gtkw Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00