Luke Wren 278dc8b6a2 meie0 default to all-zeroes		2021-06-04 07:37:02 +01:00
..
arith	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
Makefile	Rename hazard5 -> hazard3	2021-05-21 03:46:29 +01:00
hazard3.f	More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus	2021-05-29 18:00:43 +01:00
hazard3_config.vh	Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0	2021-05-31 17:54:12 +01:00
hazard3_config_inst.vh	Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0	2021-05-31 17:54:12 +01:00
hazard3_core.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_cpu_1port.v	Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0	2021-05-31 17:54:12 +01:00
hazard3_cpu_2port.v	Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0	2021-05-31 17:54:12 +01:00
hazard3_csr.v	meie0 default to all-zeroes	2021-06-04 07:37:02 +01:00
hazard3_decode.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_frontend.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_instr_decompress.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_ops.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
hazard3_regfile_1w2r.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_width_const.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
rv_opcodes.vh	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00