Luke Wren c57e9f4c9b Coding style change for Verilator compatibility (fixes #21) ... The boundary_conditions process in hazard3_frontend needs to be scheduled at least twice to resolve to the correct values. There are multiple possible interleavings, which should all result in the same result. However Verilator schedules the process only once. Work around this by moving the tie-off of the problematic variable into the synchronous update process.		2024-12-09 05:35:34 +00:00
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arith	Fix partial case overlap lint for shared A/Zbb ALU ops	2024-06-06 06:58:59 +01:00
debug	Fix abstract access GPR command using wrong register number when initiated by abstractauto.	2024-10-12 19:35:13 +01:00
hazard3.f	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_config.vh	Avoid zero-total-width concatenations for parameters parameterised	2024-05-26 16:47:20 +01:00
hazard3_config_inst.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
hazard3_core.v	PPA: predecode stage 2 bypass mux controls at end of stage 1	2024-06-06 08:36:55 +01:00
hazard3_cpu_1port.v	Fix use of non-always-on clock for arbitration of load/store vs SBA,	2024-03-17 05:46:01 +00:00
hazard3_cpu_2port.v	Fix use of non-always-on clock for arbitration of load/store vs SBA,	2024-03-17 05:46:01 +00:00
hazard3_csr.v	Set misa.b when all of Zba, Zbb and Zbs are enabled.	2024-05-11 12:13:35 +01:00
hazard3_csr_addr.vh	First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.	2022-08-22 08:47:03 +01:00
hazard3_decode.v	Fix fence.i being marked invalid in debug mode.	2024-06-01 15:38:33 +01:00
hazard3_frontend.v	Coding style change for Verilator compatibility (fixes #21)	2024-12-09 05:35:34 +00:00
hazard3_instr_decompress.v	Fix case overlap lint in instr_decompress. Now verilator lint clean	2024-06-06 07:18:52 +01:00
hazard3_irq_ctrl.v	Remove redundant masking of meinext_irq field	2024-08-01 08:45:26 +01:00
hazard3_ops.vh	Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains	2022-08-06 23:02:08 +01:00
hazard3_pmp.v	Fix verilator lint width issues in triggers, PMP, DM.	2024-05-29 15:32:45 +01:00
hazard3_power_ctrl.v	Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.	2022-11-05 18:26:56 +00:00
hazard3_regfile_1w2r.v	Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression	2022-09-04 23:56:14 +01:00
hazard3_triggers.v	Fix verilator lint width issues in triggers, PMP, DM.	2024-05-29 15:32:45 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00