Luke Wren 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. ... Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.		2021-12-07 19:24:53 +00:00
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bus_compliance_2port	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.	2021-12-07 19:24:53 +00:00
common	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.	2021-12-07 19:24:53 +00:00
instruction_fetch_match	Add instruction fetch match check	2021-05-30 11:22:36 +01:00
riscv-formal	Use .f for riscv-formal tb dependencies, small reshuffling of directories	2021-05-30 09:44:57 +01:00
.gitignore	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00