Hazard3/test/sim/rvcpp
Luke Wren a6558e554a Set misa.b when all of Zba, Zbb and Zbs are enabled.
(The B extension has now been ratified as this combination of extensions.)
2024-05-11 12:13:35 +01:00
..
include Add dummy h3.msleep CSR to rvcpp 2024-05-11 11:02:01 +01:00
.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass. 2024-03-22 00:52:01 +00:00
main.cpp Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass. 2024-03-22 00:52:01 +00:00
rv_core.cpp Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode). 2024-04-27 20:48:30 +01:00
rv_csr.cpp Set misa.b when all of Zba, Zbb and Zbs are enabled. 2024-05-11 12:13:35 +01:00