Luke Wren
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a6558e554a
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Set misa.b when all of Zba, Zbb and Zbs are enabled.
(The B extension has now been ratified as this combination of extensions.)
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2024-05-11 12:13:35 +01:00 |
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Luke Wren
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6db1edc675
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Add dummy h3.msleep CSR to rvcpp
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2024-05-11 11:02:01 +01:00 |
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Luke Wren
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194c9a9052
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Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode).
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2024-04-27 20:48:30 +01:00 |
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Luke Wren
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78260e86e7
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rvcpp: parameterise number of PMP regions, and set to match tb default. Fix region locking. Mask pmpaddr to 30 bits, to match Hazard3 32-bit physical address space.
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2024-04-27 19:57:18 +01:00 |
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Luke Wren
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ebe5a44454
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rvcpp: fix up PMP address mask for all-ones pmpaddr, and raise instruction fault on instruction stradding two PMP regions, like the hardware
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2024-04-27 19:34:17 +01:00 |
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Luke Wren
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fce1c087d4
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Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests
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2024-04-27 13:38:10 +01:00 |
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Luke Wren
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117c52e7b1
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rvcpp: fix handling of CSR instructions which both read and write
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2024-04-27 13:30:34 +01:00 |
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Luke Wren
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a313493371
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Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass.
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2024-03-22 00:52:01 +00:00 |
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Luke Wren
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b1be56fe94
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Clean up rvcpp file structure
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2024-03-21 23:27:01 +00:00 |
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Luke Wren
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b473575b7e
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rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
Also, grab the special-case core RAM change from the Sv32 fork, for better performance
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2024-03-21 00:33:54 +00:00 |
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Luke Wren
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fd584ea24b
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Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm
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2024-03-20 23:45:30 +00:00 |
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Luke Wren
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8cbf5fceee
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rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes
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2024-03-20 01:37:04 +00:00 |
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Luke Wren
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55504fa8f3
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Add support for Zba, Zbb, Zbc, Zbs, Zbkb to rvcpp. Passes tests
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2024-03-20 01:06:13 +00:00 |
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Luke Wren
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e1bb341876
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Add support for testcase return code propagation to rvcpp.
Hook up mtvec in bitmanip testcases to exit sim when exception taken.
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2024-03-20 01:05:24 +00:00 |
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Luke Wren
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32f65fb142
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Expand rvcpp counter CSR implementation
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2024-03-19 08:44:24 +00:00 |
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Luke Wren
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a536e3baa7
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rvcpp sim: add A extension and M-mode traps
(now passes a lot of the Hazard3 tests)
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2023-04-01 08:21:43 +01:00 |
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Luke Wren
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26d699e18c
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rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15
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2023-04-01 06:02:45 +01:00 |
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Luke Wren
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8f461b63b4
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Fix mvsa01/mva01s in rvcpp
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2023-03-21 21:54:04 +00:00 |
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Luke Wren
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410d002372
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First pass at adding Zcmp to rvcpp
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2023-03-21 21:28:49 +00:00 |
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Luke Wren
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8e7e8f4008
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Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance.
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2023-03-21 19:38:46 +00:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |