Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
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riscv-formal@8bede6ceb9	Use .f for riscv-formal tb dependencies, small reshuffling of directories	2021-05-30 09:44:57 +01:00
tb	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00