Hazard3/test/sim/common
Luke Wren 954bae5cf1 Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb. 2022-08-29 14:52:01 +01:00
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hazard3_csr.h Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-07 22:04:42 +01:00
hazard3_instr.h Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb. 2022-08-29 14:52:01 +01:00
hazard3_irq.h Add top/bottom-half IRQ test 2022-08-10 00:09:13 +01:00
init.S Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00
irq_dispatch.S Add test for IRQ force array 2022-08-09 23:38:14 +01:00
memmap.ld Add RISC-V debug tests 2021-07-22 17:50:04 +01:00
src_only_app.mk Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb_cxxrtl_io.h Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00