..
arith
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
debug
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
peri
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
hazard3.f
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
hazard3_config.vh
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
hazard3_config_inst.vh
Sketch in PMP implementation
2022-05-23 18:06:23 +01:00
hazard3_core.v
Fix two PMP-related bugs:
2022-05-25 13:23:44 +01:00
hazard3_cpu_1port.v
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
hazard3_cpu_2port.v
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
hazard3_csr.v
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
hazard3_csr_addr.vh
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
hazard3_decode.v
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
hazard3_frontend.v
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
hazard3_instr_decompress.v
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
hazard3_ops.vh
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
hazard3_pmp.v
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
hazard3_regfile_1w2r.v
Remove unused FAKE_DUALPORT option from regfile
2022-05-23 16:22:01 +01:00
hazard3_width_const.vh
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
rv_opcodes.vh
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00