Hazard3

History

Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
..
diagrams	Finish documenting CSRs. Draw a debug topology diagram.	2021-11-28 08:17:23 +00:00
sections	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
Makefile	Document some IRQ CSRs, and instruction timings	2021-05-31 15:57:05 +01:00
Readme.md	Document some IRQ CSRs, and instruction timings	2021-05-31 15:57:05 +01:00
hazard3.adoc	Finish documenting CSRs. Draw a debug topology diagram.	2021-11-28 08:17:23 +00:00
hazard3.pdf	Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.	2021-12-12 20:50:26 +00:00

Building

# Get tools
sudo apt install ruby-asciidoctor-pdf
# Build
make