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Hazard3/hdl
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Luke Wren f23ec3f941 Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere 2021-05-29 18:57:43 +01:00
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arith Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
Makefile Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3.f More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_config.vh Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_config_inst.vh Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_core.v Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere 2021-05-29 18:57:43 +01:00
hazard3_cpu_1port.v Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_cpu_2port.v Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_csr.v Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere 2021-05-29 18:57:43 +01:00
hazard3_decode.v More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_frontend.v More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_instr_decompress.v Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_ops.vh Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 2021-05-23 11:59:46 +01:00
hazard3_regfile_1w2r.v Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00
hazard3_rvfi_monitor.vh More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_rvfi_wrapper.v More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
hazard3_width_const.vh Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 2021-05-23 11:59:46 +01:00
rv_opcodes.vh Import from hazard5 9743a1b 2021-05-21 02:34:16 +01:00