Luke Wren f4952ab66d Add simple example SoC, hangs nextpnr for some reason!		2021-07-13 03:40:06 +01:00
..
arith	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
debug	Sync doc updates	2021-07-12 22:13:31 +01:00
hazard3.f	More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus	2021-05-29 18:00:43 +01:00
hazard3_config.vh	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_config_inst.vh	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_core.v	Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference	2021-07-13 01:10:55 +01:00
hazard3_cpu_1port.v	Add simple example SoC, hangs nextpnr for some reason!	2021-07-13 03:40:06 +01:00
hazard3_cpu_2port.v	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_csr.v	Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode	2021-07-10 21:02:18 +01:00
hazard3_decode.v	Start hacking in debug support to the core -- seems to work as well as before adding debug!	2021-07-10 18:53:48 +01:00
hazard3_frontend.v	Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode	2021-07-10 21:02:18 +01:00
hazard3_instr_decompress.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_ops.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
hazard3_regfile_1w2r.v	Some cleanup; correctly decode 16-bit EBREAK	2021-06-03 20:03:43 +01:00
hazard3_width_const.vh	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
rv_opcodes.vh	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00