Hazard3/example_soc/fpga
Luke Wren 1fa773c67a Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently. 2021-12-05 02:16:54 +00:00
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fpga_icebreaker.f Add activity LED to iCEBreaker 2021-07-25 13:13:41 +01:00
fpga_icebreaker.v Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently. 2021-12-05 02:16:54 +00:00
fpga_ulx3s.f Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k 2021-07-25 13:41:04 +01:00
fpga_ulx3s.v Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k 2021-07-25 13:41:04 +01:00
pll_25_40.v Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k 2021-07-25 13:41:04 +01:00
pll_25_50.v Tweaks to example soc configuration 2021-07-23 23:08:23 +01:00