Modify RAM and ROM to WIDTH=12 4K Byte.
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				|  | @ -8,8 +8,8 @@ SECTIONS | |||
|   .text_init   : { *(.text_init*) } | ||||
|   .text   : { *(.text*) } | ||||
|   _end = .; | ||||
|   . = 0x80004000; | ||||
|   .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; } | ||||
|   . = 0xf0040000; | ||||
|   .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; } | ||||
|   .bss : { *(.bss) } | ||||
|   . = 0xd0580000; | ||||
|   .data.io   : { *(.data.io) } | ||||
|  |  | |||
|  | @ -8,8 +8,8 @@ SECTIONS | |||
|   .text_init   : { *(.text_init*) } | ||||
|   .text   : { *(.text*) } | ||||
|   _end = .; | ||||
|   . = 0x4000; | ||||
|   .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; } | ||||
|   . = 0x800; | ||||
|   .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; } | ||||
|   .bss : { *(.bss) } | ||||
|   . = 0xd0580000; | ||||
|   .data.io   : { *(.data.io) } | ||||
|  |  | |||
|  | @ -53,7 +53,7 @@ module axi_slv #( | |||
|     output reg [TAGW-1:0] bid | ||||
| ); | ||||
| 
 | ||||
|   parameter MEM_DEPTH = 15;  // memory size = 0x8000 = 32k
 | ||||
|   parameter MEM_DEPTH = 12;  // memory size = 0x8000 = 32k WIDTH=15
 | ||||
| 
 | ||||
|   bit [7:0] mem[(1<<MEM_DEPTH)-1:0]; | ||||
| 
 | ||||
|  |  | |||
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