315adcf076
Integrate api trace into tim-vx source as an experimental feature. ( #623 )
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* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
2023-07-19 18:40:48 +08:00
f728e1b42d
Update overview diagram
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
7d88a668e3
Update internal for 22Q2 release ( #432 )
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* Update internal for 22Q2 release
update to internal commit-id: e96103281b08404cabb9b65306587627cfa3cb93
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
* Update prebuilt for 22Q2 release
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-07-25 09:29:22 +08:00
e27e15925c
Add unidirectional sequence lstm support
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-08-09 13:43:33 +08:00
e24324ed42
Update gitignore
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-11 12:53:31 +08:00
def53f4b5c
Update internal to REL/v1.1.30
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Commit: 6ccb425e
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-02-26 17:05:14 +08:00
MercuryChen
ZhangXiang
liyuenan
Kainan Cha
Jiang Bo