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307 Commits

Author SHA1 Message Date
Dahan Gong aaaeda1846
doc: fix some comments (#322) 2022-03-17 12:21:20 +08:00
Kee 2a8936dfed
Added unit test for batch2space and space2batch (#321) 2022-03-15 21:25:01 +08:00
Zhouheng Zheng 4d5013edf9
wrapper public ovxlib api (#320) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-15 21:24:15 +08:00
Zhouheng Zheng b02aa8b8c4
Added customize operator APIs(#315) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-09 12:10:08 +08:00
Zhouheng Zheng 161bb8a7c4
Pre-release for 22Q1 (#302) 
update internal to commit-id: d45da6fa

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-01 17:56:03 +08:00
Sven e63059857b
Update reshape to reshape2 (#310) 
Update built-in op reshape to reshape2

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 17:04:02 +08:00
Sven c8a25d32ad
Relax tolerance for div_uint8 case (#303) 
* Relax tolerance for Div.shape_5_1_broadcast_scale_uint8
* Add tolerance for div uint8

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 10:54:56 +08:00
chxin66 3decff5398
Added unit test for STACK (#298) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-23 22:04:54 +08:00
chxin66 242a6bd05a
Add pad value for grouped_conv1d (#292) 
https://github.com/VeriSilicon/TIM-VX/issues/284

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-21 19:11:36 +08:00
liyuenan fe31a47bf9
enable no bias in FC layout inference (#294) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-02-21 19:09:38 +08:00
Sven 6e0ac09c92
Relax tolerance for Div.shape_5_1_broadcast_scale_uint8 (#296) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-21 18:34:44 +08:00
robert-kalmar 51a3d8ce36
Install headers to place defined by CMAKE_INSTALL_INCLUDEDIR variable (#291) 2022-02-21 10:20:38 +08:00
yingshengBD f80e1b196f
Fix compile error in g++5.4 (#286) 2022-02-11 08:20:05 +08:00
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285) 
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-09 10:52:11 +08:00
SHagerAT80 1c5302ba51
Enabled bulding with buildroot toolchain. (#281) 2022-01-28 13:12:22 +08:00
Sven 86fcb0d0e0
Fix build error with gcc 6.2.0 (#282) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-27 11:42:12 +08:00
Sven 19e4e86651
Support NPU access large memory > 4G (#280) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-26 16:00:14 +08:00
chxin66 9fdba427f7
Integrate benchmark test of conv2d and depthwise conv2d (#276) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-21 15:32:23 +08:00
chxin66 3b11a6a5b2
Added a matmul unit_test for issue 271 (#278) 
https://github.com/VeriSilicon/TIM-VX/issues/271

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 22:35:44 +08:00
chxin66 32308f62c5
Add softmax unit test (#274) 
https://github.com/VeriSilicon/TIM-VX/issues/266

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 14:54:39 +08:00
Sven a02900d135
Fix regression introduced by V1.1.37 update (#275) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-18 11:36:09 +08:00
Sven 04cd392b7e
Refine readme (#273) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-17 18:22:39 +08:00
Sven e6eeb5dbee
Update component diagram and README.md (#269) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-17 01:13:20 +08:00
onepick 7fa5223943
Disable float32 to float16 conversion by default(#267) 
Disable conversion since this will impact the precision. User should enable this conversion explicitly.

Signed-off-by: Jia <juku.jia@verisilicon.com>

Co-authored-by: Jia <juku.jia@verisilicon.com>
 2022-01-14 17:18:16 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Kainan Cha fe91e7f13d
Update README.md 
Add framework support for Paddle-Lite and OpenCV
 2022-01-12 14:39:43 +08:00
Antkillerfarm 9813a5da9a
add vxc binary for internal ops (#255) 
cmake -DUSE_VXC_BINARY=1 -DVCCOMPILER_PATH=<vcCompiler path> -DGPU_CONFIG_FILE=<gpu config file> ..
 2022-01-12 11:04:49 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2022-01-11 14:13:15 +08:00
Sven ff25226adb
[Internal] support prebuilt kernel into shared library (#260) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-11 11:45:29 +08:00
Sven c1ed45150d
Added strided_slice test case with 5D-tensor (#261) 
test case can be found
    https://github.com/VeriSilicon/TIM-VX/issues/213

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 17:06:26 +08:00
Sven 58d2c0dedc
Fix GCC5 build error (#259) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-10 01:56:36 +08:00
Sven ed47c5c24c
Update internal to 1.1.37_preview (#254) 
* update internal to V1.1.37

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update VSimulator V6.4.9 for linux x86_64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 01:56:00 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
 2022-01-04 14:35:17 +08:00
chxin66 eecbe264b6
Add a unit_test for div_uint8 (#251) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-30 13:31:30 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 15:38:42 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-22 09:47:57 +08:00
Sven e42faad710
Fix build issue if 40BIT_VA enabled (#240) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-12-17 15:00:14 +08:00
Sven 321a53fd2a
Support single static-library for libtim-vx.a (#237) 
Fix external ovxlib build failure, and change install dir to CMAKE_INSTALL_LIBDIR

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 22:23:32 +08:00
liyuenan 2c38f89d06
Catch the correct output when output has consumer (#239) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 09:54:54 +08:00
chxin66 1f85d21558
mapped signal frame & unit test (#234) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-09 10:33:40 +08:00
chxin66 dc31091db5
mapped groupedconv1d & unit test (#233) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-06 19:20:13 +08:00
Zongwu.Yang bd496219c8
Add quantize, dequantize, requantize test (#232) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-02 15:40:41 +08:00
Antkillerfarm b38bd41933
add DataLayout::IcOcWH for TVM usage (#231) 2021-11-30 21:33:14 +08:00
Antkillerfarm e001d53ddf
remove 64bit data type from doc (#230) 2021-11-29 11:02:44 +08:00
Sven 62a33ecfde
Install libtim-vx.so to lib64 if build for aarch64 (#225) 
* Install libtim-vx.so to lib64 if build for aarch64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-24 15:18:29 +08:00
Sven bc42f7987c
Fix build if lowlevel driver doesn't support DMABuffer fd (#224) 
* Fix build if lowlevel driver doesn't support DMABuffer fd

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-23 11:34:03 +08:00