33fd1f0c58
Add map for DeConv1d ( #62 )
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Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-05-24 23:41:15 +08:00
3339135c82
add docs for ops
2021-05-21 18:39:59 +08:00
be0a566042
Add map for Conv1D
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Convolution 1D operation, support float32, int8, int16, uint8.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-05-21 12:46:56 +08:00
88f7141cfe
Support LayerNormalization
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Layer normalization only support float32 data type.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-05-21 12:46:19 +08:00
c3858af4fc
Fix bazel build by warning as error ( #58 )
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-20 16:23:04 +08:00
b4b6a369a7
Add map for InstanceNormalization
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Currently instance normalization only support float32 data type.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-05-20 12:41:25 +08:00
e3b127df50
Add group parameter for deconv API ( #51 )
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* Add group parameter for deconv API
Limitation: only support depthwise deconvolution
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
* Add single channel case and fix build warning
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-20 10:56:52 +08:00
7c0d2f59bb
Update op README
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-20 06:15:46 +08:00
b1b7eadefc
Add group parameter for deconv API
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Limitation: only support depthwise deconvolution
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-20 06:15:28 +08:00
baea9b827f
Add ANEURALNETWORKS API reference
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-18 14:24:17 +08:00
7770a8fd91
Update Op README
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-18 02:07:52 +08:00
e05b6f7404
Update operation README with reference
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These links are for reference only, actually implementation
may vary in terms of dimensions and parameters supported.
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-18 01:58:08 +08:00
66dd29703e
Refine cmake build: add gtest ( #47 )
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-17 13:04:45 +08:00
cc3b8c1fe0
Support layout inference for FC and Resize ( #45 )
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-15 22:42:11 +08:00
55ef50385e
Change back the inferface name ( #44 )
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-14 20:08:53 +08:00
b38cad9f1d
Add data layout for kernel to support TVM conv2d ( #40 )
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Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-14 14:00:02 +08:00
748274143b
support layout inference for operations ( #39 )
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Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-13 22:27:23 +08:00
ef69e466c7
Move all UT to tim/vx/ut directory
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-12 16:32:40 +08:00
301d88a5a6
Add support for relational ops
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-11 23:39:22 +08:00
d92e08e502
Add support for Cast and Floor operation
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-11 18:45:28 +08:00
2b29d5d41c
Fix file permission
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-11 11:01:21 +08:00
c2e10efb50
Add support for Reorg
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The Reorg implementation is that of YOLOv2.
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-05-11 10:57:56 +08:00
77b801a590
Add layout inference feature ( #34 )
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* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-08 09:29:47 +08:00
eff71c38bf
add argmin and argmax op
2021-04-16 00:34:29 +08:00
c9d3416c6b
Add the Squeeze op
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-04-15 11:22:48 +08:00
dc67e9ac63
add the Stack op
2021-04-07 19:57:28 +08:00
165b3fcf8f
Minor clean up
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Fix typos and move functions into appropriate files
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-04-07 13:03:56 +08:00
07fc3b9914
add the clip, dropout, batchnorm op
2021-04-07 13:00:41 +08:00
90a52ea6c9
Add support for Mish, SoftRelu and HardSigmoid
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-31 12:00:02 +08:00
c569555f1f
Use FCL2 instead of FCL which supports axis
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-03-29 17:08:22 +08:00
b5f2666e92
Map Select
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-03-25 17:27:04 +08:00
0d7afd9d51
Minor cleanup
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-19 11:12:12 +08:00
b6f0ffaef6
Fix Mutliply API
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Internal ops require a scale parameter to be initialized
to 1.0f.
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-17 17:56:11 +08:00
8f1c33ea83
add README.md for op support
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-03-16 11:46:57 +08:00
c46904c339
Add op support for Deconv2d
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-02-26 09:54:01 +08:00
9d44b4477b
Added NBG support
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-02-22 11:38:21 +08:00
44af63b9e9
[NNRT-811]Map Slice
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-01-22 14:32:43 +08:00
0e422b1e6a
Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-01-19 16:44:43 +08:00
90b7a6fc32
Rename Op 'Permute' to 'Transpose'
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-12 11:21:51 +08:00
7972af0697
Initial Commit for VERSION 1.1.28
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-11 18:27:48 +08:00
Nightingale
jing.tang
zhao.xia
Sven
Kainan Cha
liyuenan
Zongwu.Yang
zhengzhouheng
yuenan.li
Kainan Cha
Jiang Bo