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165 Commits

Author SHA1 Message Date
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 58395cf7a7 Modified bidirectional_sequence_lstm golden accuracy 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:26:07 +08:00
root 80fed36ea3 Modified Div_int unit test golden 
Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
 2022-08-30 10:28:09 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
Chen Xin 03b5ec2d17 Added div int32 unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 14:37:34 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
Chen Xin 27b4298b29 Fixed quantize param in reduce_sum 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-29 11:12:09 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00
chxin66 96c9d5df01
Added cases for reduce sum (#441) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:53:56 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
chxin66 6344379469
Disabled 3 failed case (#428) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:54:42 +08:00
chxin66 e047fce59f
Disable cases which offloaded to SW path(#422) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-04 15:37:06 +08:00
Antkillerfarm 3dd6c507d4
add reshape unit test (#416) 2022-06-23 14:07:38 +08:00
MESeraph 11f953b506
Mapped roi_pool & added unit test (#404) 
* Mapped roi_pool & added unit test

* modify roialign/roipool unit test
 2022-05-30 19:57:50 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
MESeraph 6d0c6b01b5
modify GatherElements (#406) 2022-05-29 22:25:14 +08:00
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-27 16:34:48 +08:00
Sven a9764291b0
Fix build issue (#397) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-16 14:24:44 +08:00
chxin66 0d8ac3dc2b
Added gather_elements & unit test (#363) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-10 09:55:50 +08:00
Antkillerfarm c6847981e6
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for unit test compatibility (#386) 2022-05-06 09:30:26 +08:00
MESeraph eab0d807a6
Added Ceil & unit test (#381) 
* Added Ceil & unit test

* Added Round & Unit test
 2022-05-05 17:11:31 +08:00
chxin66 7a8ae32f73
Added topk & unit test (#384) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:06:39 +08:00
Zhouheng Zheng c09cdf79ad
fix bug of param num in custom op (#385) 
ref to:https://github.com/VeriSilicon/TIM-VX/issues/378

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-05-05 17:04:38 +08:00
Antkillerfarm 3f2e67b65f
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for ovxlib compatibility (#374) 2022-04-24 18:38:56 +08:00
Sven b5c4514b94
Update operator support planw (#367) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-04-19 11:38:07 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00
chxin66 ba6b311409
Added hardsigmoid test case with alpha and beta (#356) 
https://github.com/VeriSilicon/TIM-VX/issues/306

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:10:30 +08:00
chxin66 c033cfc582
Fixed compiler fail for elu (#358) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 18:42:50 +08:00
chxin66 e8ca6b8ee3
Added param step for slice & added unit test (#352) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 15:42:58 +08:00
chxin66 d0af7ae8df
Support alpha in elu (#354) 
https://github.com/VeriSilicon/TIM-VX/issues/305

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-11 19:04:30 +08:00
Zhouheng Zheng b4091318ea
fix buf of param init in custom op (#345) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-04-06 17:21:54 +08:00
chxin66 1ca89d2ffa
Add layout inference & layout test for stack (#337) 
* Added layout inference & layout test for stack

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-06 13:01:41 +08:00
Sven 171abb0f1b
Revert "composed Dense & added unit test (#312)" (#340) 
This reverts commit f2e71a3deb.
 2022-03-31 18:37:45 +08:00
chxin66 f2e71a3deb
composed Dense & added unit test (#312) 
if shape is 3D or larger, implement it as reshape + fc + reshape

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-03-25 10:49:39 +08:00
Kee 53291e99cf
Add ArgMax/ArgMin unit tests (#333) 
* Add ArgMax/ArgMin unit tests

https://github.com/VeriSilicon/TIM-VX/issues/330
 2022-03-25 09:46:50 +08:00
Sven 097f8d74cd
Refine customized op support (#327) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 23:00:52 +08:00
Sven 08500158ba
Fix build error with clang (#326) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 14:51:12 +08:00
Kee 2a8936dfed
Added unit test for batch2space and space2batch (#321) 2022-03-15 21:25:01 +08:00
Zhouheng Zheng 4d5013edf9
wrapper public ovxlib api (#320) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-15 21:24:15 +08:00
Zhouheng Zheng b02aa8b8c4
Added customize operator APIs(#315) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-09 12:10:08 +08:00
Sven e63059857b
Update reshape to reshape2 (#310) 
Update built-in op reshape to reshape2

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 17:04:02 +08:00
Sven c8a25d32ad
Relax tolerance for div_uint8 case (#303) 
* Relax tolerance for Div.shape_5_1_broadcast_scale_uint8
* Add tolerance for div uint8

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 10:54:56 +08:00