29f1efc492
add API 'Clone' to tim_vx op and support default layout inference
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-07-06 12:29:18 +08:00
98b9759663
Refine arg in layout inference
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-29 11:24:28 +08:00
1e42cfd668
Support layout inference for nbg
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-24 17:28:02 +08:00
f8f2c6d519
Fix layout inference for traspose convolution
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-21 17:14:16 +08:00
1f08618403
Supprt layout inference for Operations
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-02 00:53:11 +08:00
fae5cede7a
Support layout inference for ops ( #77 )
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-27 10:33:44 +08:00
410cd8e516
Refine the cmake build ( #63 )
...
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-24 13:40:37 +08:00
66dd29703e
Refine cmake build: add gtest ( #47 )
...
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-17 13:04:45 +08:00
cc3b8c1fe0
Support layout inference for FC and Resize ( #45 )
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-15 22:42:11 +08:00
b38cad9f1d
Add data layout for kernel to support TVM conv2d ( #40 )
...
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-14 14:00:02 +08:00
748274143b
support layout inference for operations ( #39 )
...
Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-05-13 22:27:23 +08:00
a42517fdce
Align directory name to namespace for layout inference ( #38 )
...
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-11 09:46:46 +08:00
yuenan.li
liyuenan
Sven
Zongwu.Yang