TIM-VX/src/tim/transform
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-28 09:45:50 +08:00
..
ops Fixed BidirectionalSequenceRnn bugs 2022-11-28 09:45:50 +08:00
average_pool_layout_infer_test.cc Fixed average pool layout infer 2022-11-16 13:34:31 +08:00
layout_infer_context.h Catch the correct output when output has consumer (#239) 2021-12-15 09:54:54 +08:00
layout_inference.cc Fixed BidirectionalSequenceRnn bugs 2022-11-28 09:45:50 +08:00
layout_inference_test.cc Align directory name to namespace for layout inference (#38) 2021-05-11 09:46:46 +08:00
pad_layout_inference_test.cc Fixed pad layout inference bug & added one stridedslice case (#370) 2022-04-20 21:44:43 +08:00
permute_vector.h Align directory name to namespace for layout inference (#38) 2021-05-11 09:46:46 +08:00
reduce_layout_inference_test.cc Added two reduce layout infer unittest 2022-09-28 09:37:38 +08:00
rnncell_layout_inference_test.cc Supported composed layout infer & added unit test 2022-09-26 14:29:46 +08:00
stack_layout_inference_test.cc Disable cases which offloaded to SW path(#422) 2022-07-04 15:37:06 +08:00
stridedslice_layout_inference_test.cc Fixed pad layout inference bug & added one stridedslice case (#370) 2022-04-20 21:44:43 +08:00