78 lines
1.8 KiB
Bash
78 lines
1.8 KiB
Bash
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#!/bin/bash
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# if [ $# -ne 1 -o ! -d "$1" ]; then
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# echo "Usage: $0 <design>" >&2
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# exit 1
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# fi
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set -ex
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PWD=$(pwd)
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SOC=$PWD/../../soc
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design=${1%/}
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YOSYS_COARSE=true
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YOSYS_GLOBRST=false
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YOSYS_SPLITNETS=false
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TOP="soc_top"
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RTL=$(cat ../../soc/soc_top.mk)
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rtl_files=""
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for src in $RTL; do
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rtl_files="$rtl_files $SOC/$src"
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done
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mkdir -p gen
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rm -rf gen/*
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mkdir gen/design
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BUILD_PATH=gen/ PERLLIB=${SOC} ${SOC}/swerv.config -target=default -set iccm_enable
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filelist=""
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for file in $rtl_files; do
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filelist="$filelist $file"
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done
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sv2v -Igen -I/home/colin/develop/AbstractAccelerator/Cores-SweRV/design/include \
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gen/common_defines.vh $filelist > gen/soc_top.v
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{
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# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
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# for file in $rtl_files; do
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# echo "read_verilog -sv -I../../design/include $file"
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# done
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echo "read_verilog gen/soc_top.v"
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if test -n "$TOP"; then
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echo "hierarchy -check -top $TOP"
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else
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echo "hierarchy -check"
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fi
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if $YOSYS_GLOBRST; then
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# insertation of global reset (e.g. for FPGA cores)
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echo "add -global_input globrst 1"
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echo "proc -global_arst globrst"
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fi
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echo "synth -run coarse; opt -fine"
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# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
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if ! $YOSYS_COARSE; then
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echo "memory_map; techmap; opt; abc -dff; clean"
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fi
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if $YOSYS_SPLITNETS; then
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# icarus verilog has a performance problems when there are
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# dependencies between the bits of a long vector
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echo "splitnets; clean"
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fi
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if $YOSYS_COARSE; then
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echo "write_verilog -noexpr -noattr gen/synth.v"
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else
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echo "select -assert-none t:\$[!_]"
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echo "write_verilog -noattr gen/synth.v"
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fi
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echo "synth_ecp5 -top $TOP -json gen/soc.json"
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# echo "synth_xilinx -top $TOP"
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} > gen/synth.ys
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yosys -v2 -l gen/synth.log gen/synth.ys
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nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json
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