32 lines
634 B
Systemverilog
32 lines
634 B
Systemverilog
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module bram(
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input clk,
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input re,
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input we,
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input [DEPTH-1:0] addr_rd,
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input [DEPTH-1:0] addr_wr,
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output logic [WIDTH-1:0] data_rd,
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input [WIDTH-1:0] data_wr
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);
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parameter WIDTH=8;
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parameter DEPTH=8;
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parameter SIZE=(1<<DEPTH);
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logic [WIDTH-1:0] ram [0:SIZE-1];
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initial begin
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$readmemh("data.bin", ram);
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end
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always @(posedge clk) begin
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if (we) begin
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ram[addr_wr] <= data_wr;
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end
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end
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always @(posedge clk) begin
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if (re) begin
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data_rd <= ram[addr_rd];
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end
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end
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endmodule
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