28 lines
457 B
Coq
28 lines
457 B
Coq
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module soc_sim (
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input bit core_clk
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);
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logic rst_l;
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parameter MAX_CYCLES = 1000;
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// parameter MAX_CYCLES = 10_000_000_0;
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int cycleCnt;
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always @(posedge core_clk) begin
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cycleCnt <= cycleCnt + 1;
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if (cycleCnt == MAX_CYCLES) begin
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$display("Hit max cycle count (%0d) .. stopping", cycleCnt);
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$finish;
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end
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end
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assign rst_l = cycleCnt > 5;
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soc_top rvsoc (
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.clk(core_clk),
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.rst(rst_l)
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);
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endmodule
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