312 lines
9.3 KiB
Coq
312 lines
9.3 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module mem_ctrl(
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haddr_s1,
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hburst_s1,
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hprot_s1,
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hrdata_s1,
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hready_s1,
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hresp_s1,
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hsel_s1,
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hsize_s1,
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htrans_s1,
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hwdata_s1,
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hwrite_s1,
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pad_cpu_rst_b,
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pll_core_cpuclk
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);
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// &Ports; @25
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input [31:0] haddr_s1;
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input [2 :0] hburst_s1;
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input [3 :0] hprot_s1;
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input hsel_s1;
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input [2 :0] hsize_s1;
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input [1 :0] htrans_s1;
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input [31:0] hwdata_s1;
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input hwrite_s1;
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input pad_cpu_rst_b;
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input pll_core_cpuclk;
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output [31:0] hrdata_s1;
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output hready_s1;
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output [1 :0] hresp_s1;
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// &Wires; @26
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wire ahb_trans_clear;
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wire ahb_trans_valid;
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wire bypass_if_write_byte;
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wire bypass_if_write_hword;
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wire bypass_if_write_word;
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wire [31:0] haddr;
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wire [31:0] haddr_s1;
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wire hclk;
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wire [31:0] hrdata;
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wire [31:0] hrdata_pre;
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wire [31:0] hrdata_s1;
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wire hready_s1;
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wire [1 :0] hresp_s1;
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wire hrst_b;
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wire hsel;
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wire hsel_s1;
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wire [2 :0] hsize;
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wire [2 :0] hsize_s1;
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wire [1 :0] htrans;
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wire [1 :0] htrans_s1;
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wire [31:0] hwdata;
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wire [31:0] hwdata_s1;
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wire hwrite;
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wire hwrite_s1;
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wire pad_cpu_rst_b;
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wire pll_core_cpuclk;
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wire [14:0] ram0_addr;
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wire [7 :0] ram0_din;
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wire [7 :0] ram0_dout;
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wire [14:0] ram1_addr;
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wire [7 :0] ram1_din;
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wire [7 :0] ram1_dout;
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wire [14:0] ram2_addr;
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wire [7 :0] ram2_din;
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wire [7 :0] ram2_dout;
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wire [14:0] ram3_addr;
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wire [7 :0] ram3_din;
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wire [7 :0] ram3_dout;
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wire [31:0] ram_addr;
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wire ram_clk;
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wire [3 :0] ram_wen_byte;
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wire [3 :0] ram_wen_hword;
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wire [3 :0] ram_wen_word;
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wire raw_bypass_en;
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wire raw_en;
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wire raw_no_bypass;
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wire rdata_vld;
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wire read_en;
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wire write_en;
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// &Regs; @27
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reg [31:0] haddr_ff;
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reg [31:0] hrdata_raw;
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reg hread_ff;
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reg hready;
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reg [1 :0] hresp;
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reg [2 :0] hsize_ff;
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reg hwrite_ff;
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reg [3 :0] ram_wen;
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reg [3 :0] ram_wen_pre;
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reg raw_data_vld;
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// &Force("input", "hburst_s1"); @29
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// &Force("input", "hprot_s1"); @30
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// &Force("bus", "hburst_s1", 2, 0); @31
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// &Force("bus", "hprot_s1", 3, 0); @32
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parameter MEM_ADDR_WIDTH = 17;
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assign hclk = pll_core_cpuclk;
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assign hrst_b = pad_cpu_rst_b;
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assign hsel = hsel_s1;
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assign htrans[1:0] = htrans_s1[1:0];
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assign hsize[2:0] = hsize_s1[2:0];
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assign haddr[31:0] = haddr_s1[31:0];
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assign hwrite = hwrite_s1;
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assign hresp_s1[1:0] = hresp[1:0];
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assign hready_s1 = hready;
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assign hwdata[31:0] = hwdata_s1[31:0];
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assign hrdata_s1[31:0] = hrdata[31:0];
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assign ahb_trans_valid = hsel && hready &&
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((htrans[1:0] == 2'b10) || (htrans[1:0] == 2'b11));
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assign ahb_trans_clear = hready && !hsel;
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always @(posedge hclk or negedge hrst_b)
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begin
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if (!hrst_b)
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begin
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hwrite_ff <= 1'b0;
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hread_ff <= 1'b0;
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hsize_ff[2:0] <= 3'd0;
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haddr_ff[31:0] <= 32'd0;
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raw_data_vld <= 1'b0;
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end
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else if (ahb_trans_valid)
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begin
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hwrite_ff <= hwrite;
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hread_ff <= !hwrite;
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hsize_ff[2:0] <= hsize[2:0];
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haddr_ff[31:0] <= haddr[31:0];
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raw_data_vld <= raw_bypass_en;
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end
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else if (ahb_trans_clear)
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begin
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hwrite_ff <= 1'b0;
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hread_ff <= 1'b0;
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hsize_ff[2:0] <= 3'd0;
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haddr_ff[31:0] <= 32'd0;
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raw_data_vld <= 1'b0;
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end
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end
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assign write_en = hwrite_ff;
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assign read_en = ahb_trans_valid && !hwrite;
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assign rdata_vld = hread_ff;
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assign raw_en = write_en && read_en;
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// =============================================
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// AHB bus response
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// =============================================
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always @(posedge hclk or negedge hrst_b)
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begin
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if (!hrst_b)
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hresp[1:0] <= 2'b00;
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else
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hresp[1:0] <= 2'b00;
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end
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assign raw_no_bypass = raw_en && (!raw_bypass_en);
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always @(posedge hclk or negedge hrst_b)
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begin
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if (!hrst_b)
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hready <= 1'b0;
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else if (raw_no_bypass)
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hready <= 1'b0;
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else
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hready <= 1'b1;
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end
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assign ram_addr[31:0] = (write_en || !hready) ? haddr_ff[31:0] : haddr[31:0];
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// =============================================
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// data input and output distribution and reform
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// =============================================
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assign ram_clk = hclk;
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assign ram0_addr[MEM_ADDR_WIDTH-3:0] = ram_addr[MEM_ADDR_WIDTH-1:2];
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assign ram1_addr[MEM_ADDR_WIDTH-3:0] = ram_addr[MEM_ADDR_WIDTH-1:2];
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assign ram2_addr[MEM_ADDR_WIDTH-3:0] = ram_addr[MEM_ADDR_WIDTH-1:2];
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assign ram3_addr[MEM_ADDR_WIDTH-3:0] = ram_addr[MEM_ADDR_WIDTH-1:2];
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assign ram_wen_byte[0] = (haddr[1:0] == 2'h0);
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assign ram_wen_byte[1] = (haddr[1:0] == 2'h1);
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assign ram_wen_byte[2] = (haddr[1:0] == 2'h2);
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assign ram_wen_byte[3] = (haddr[1:0] == 2'h3);
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assign ram_wen_hword[0] = (haddr[1] == 1'd0);
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assign ram_wen_hword[1] = (haddr[1] == 1'd0);
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assign ram_wen_hword[2] = (haddr[1] == 1'd1);
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assign ram_wen_hword[3] = (haddr[1] == 1'd1);
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assign ram_wen_word[3:0] = 4'hf;
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always @( * )
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begin
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case (hsize[2:0])
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3'b000: // byte
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ram_wen_pre[3:0] = ram_wen_byte[3:0];
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3'b001: // half-word
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ram_wen_pre[3:0] = ram_wen_hword[3:0];
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3'b010: // word
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ram_wen_pre[3:0] = ram_wen_word[3:0];
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default:
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ram_wen_pre[3:0] = 4'b0;
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endcase
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end
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always @(posedge hclk or negedge hrst_b)
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begin
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if (!hrst_b)
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ram_wen[3:0] <= 4'b0;
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else if (ahb_trans_valid && hwrite)
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ram_wen[3:0] <= ram_wen_pre[3:0];
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else
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ram_wen[3:0] <= 4'b0;
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end
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assign ram0_din[7:0] = hwdata[7:0];
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assign ram1_din[7:0] = hwdata[15:8];
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assign ram2_din[7:0] = hwdata[23:16];
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assign ram3_din[7:0] = hwdata[31:24];
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assign bypass_if_write_word = (haddr_ff[MEM_ADDR_WIDTH-1:2] == haddr[MEM_ADDR_WIDTH-1:2]) &&
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(hsize_ff[1:0] == 2'b10);
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assign bypass_if_write_hword = (haddr_ff[MEM_ADDR_WIDTH-1:1] == haddr[MEM_ADDR_WIDTH-1:1]) &&
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(hsize_ff[1:0] == 2'b01) && (!hsize[1]);
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assign bypass_if_write_byte = (haddr_ff[MEM_ADDR_WIDTH-1:0] == haddr[MEM_ADDR_WIDTH-1:0]) &&
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(hsize[1:0] == 2'b00);
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assign raw_bypass_en = raw_en && (bypass_if_write_word ||
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bypass_if_write_hword ||
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bypass_if_write_byte);
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assign hrdata_pre[31:0] = rdata_vld ? {ram3_dout[7:0], ram2_dout[7:0], ram1_dout[7:0], ram0_dout[7:0]} : 32'b0;
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always @(posedge hclk or negedge hrst_b)
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begin
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if (!hrst_b)
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hrdata_raw[31:0] <= 32'd0;
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else if (raw_bypass_en)
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hrdata_raw[31:0] <= hwdata[31:0];
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else
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hrdata_raw[31:0] <= hrdata_raw[31:0];
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end
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assign hrdata[31:0] = raw_data_vld ? hrdata_raw[31:0] : hrdata_pre[31:0];
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soc_fpga_ram #(8, MEM_ADDR_WIDTH-2) ram0(
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.PortAClk (ram_clk),
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.PortAAddr(ram0_addr),
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.PortADataIn (ram0_din),
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.PortAWriteEnable(ram_wen[0]),
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.PortADataOut(ram0_dout));
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soc_fpga_ram #(8, MEM_ADDR_WIDTH-2) ram1(
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.PortAClk (ram_clk),
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.PortAAddr(ram1_addr),
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.PortADataIn (ram1_din),
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.PortAWriteEnable(ram_wen[1]),
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.PortADataOut(ram1_dout));
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soc_fpga_ram #(8, MEM_ADDR_WIDTH-2) ram2(
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.PortAClk (ram_clk),
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.PortAAddr(ram2_addr),
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.PortADataIn (ram2_din),
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.PortAWriteEnable(ram_wen[2]),
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.PortADataOut(ram2_dout));
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soc_fpga_ram #(8, MEM_ADDR_WIDTH-2) ram3(
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.PortAClk (ram_clk),
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.PortAAddr(ram3_addr),
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.PortADataIn (ram3_din),
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.PortAWriteEnable(ram_wen[3]),
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.PortADataOut(ram3_dout));
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// &Force("nonport", "ram0_addr"); @212
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// &Force("nonport", "ram1_addr"); @213
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// &Force("nonport", "ram2_addr"); @214
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// &Force("nonport", "ram3_addr"); @215
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// &Force("nonport", "ram0_din"); @216
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// &Force("nonport", "ram1_din"); @217
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// &Force("nonport", "ram2_din"); @218
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// &Force("nonport", "ram3_din"); @219
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// &Force("nonport", "ram0_dout"); @220
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// &Force("nonport", "ram1_dout"); @221
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// &Force("nonport", "ram2_dout"); @222
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// &Force("nonport", "ram3_dout"); @223
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// &Force("nonport", "ram_wen"); @224
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// &Force("nonport", "ram_clk"); @225
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// &ModuleEnd; @227
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endmodule
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