432 lines
17 KiB
Coq
432 lines
17 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @24
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module soc(
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b_pad_gpio_porta,
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i_pad_clk,
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i_pad_jtg_nrst_b,
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i_pad_jtg_tclk,
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i_pad_jtg_tdi,
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i_pad_jtg_tms,
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i_pad_jtg_trst_b,
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i_pad_rst_b,
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i_pad_uart0_sin,
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o_pad_jtg_tdo,
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o_pad_uart0_sout
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);
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// &Ports("compare", "../src_rtl/soc_top_golden_port.v"); @25
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input i_pad_clk;
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input i_pad_jtg_nrst_b;
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input i_pad_jtg_tclk;
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input i_pad_jtg_tdi;
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input i_pad_jtg_tms;
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input i_pad_jtg_trst_b;
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input i_pad_rst_b;
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input i_pad_uart0_sin;
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output o_pad_jtg_tdo;
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output o_pad_uart0_sout;
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inout [7 :0] b_pad_gpio_porta;
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// &Regs; @26
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// &Wires; @27
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wire [7 :0] b_pad_gpio_porta;
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wire [31:0] biu_pad_haddr;
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wire [2 :0] biu_pad_hburst;
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wire [3 :0] biu_pad_hprot;
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wire [2 :0] biu_pad_hsize;
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wire [1 :0] biu_pad_htrans;
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wire [31:0] biu_pad_hwdata;
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wire biu_pad_hwrite;
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wire [1 :0] biu_pad_lpmd_b;
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wire clk_en;
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wire corec_pmu_sleep_out;
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wire cpu_clk;
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wire fifo_biu_hready;
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wire [31:0] fifo_pad_haddr;
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wire [2 :0] fifo_pad_hburst;
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wire [3 :0] fifo_pad_hprot;
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wire [2 :0] fifo_pad_hsize;
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wire [1 :0] fifo_pad_htrans;
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wire fifo_pad_hwrite;
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wire had_pad_jtg_tdo;
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wire [31:0] haddr_s1;
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wire [31:0] haddr_s2;
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wire [31:0] haddr_s3;
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wire [2 :0] hburst_s1;
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wire [2 :0] hburst_s3;
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wire hmastlock;
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wire [3 :0] hprot_s1;
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wire [3 :0] hprot_s3;
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wire [31:0] hrdata_s1;
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wire [31:0] hrdata_s2;
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wire [31:0] hrdata_s3;
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wire hready_s1;
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wire hready_s2;
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wire hready_s3;
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wire [1 :0] hresp_s1;
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wire [1 :0] hresp_s2;
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wire [1 :0] hresp_s3;
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wire hsel_s1;
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wire hsel_s2;
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wire hsel_s3;
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wire [2 :0] hsize_s1;
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wire [2 :0] hsize_s3;
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wire [1 :0] htrans_s1;
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wire [1 :0] htrans_s3;
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wire [31:0] hwdata_s1;
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wire [31:0] hwdata_s2;
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wire [31:0] hwdata_s3;
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wire hwrite_s1;
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wire hwrite_s2;
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wire hwrite_s3;
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wire i_pad_clk;
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wire i_pad_cpu_jtg_rst_b;
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wire i_pad_jtg_nrst_b;
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wire i_pad_jtg_tclk;
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wire i_pad_jtg_tdi;
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wire i_pad_jtg_tms;
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wire i_pad_jtg_trst_b;
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wire i_pad_rst_b;
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wire i_pad_uart0_sin;
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wire [1 :0] nmi_wake_int_lower;
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wire o_pad_jtg_tdo;
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wire o_pad_uart0_sout;
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wire [31:0] pad_biu_hrdata;
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wire pad_biu_hready;
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wire [1 :0] pad_biu_hresp;
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wire pad_cpu_rst_b;
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wire pad_had_jtg_tclk;
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wire pad_had_jtg_tdi;
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wire pad_had_jtg_tms;
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wire pad_had_jtg_trst_b;
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wire pad_had_jtg_trst_b_pre;
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wire [31:0] pad_vic_int_vld;
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wire per_clk;
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wire pg_reset_b;
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wire pmu_corec_isolation;
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wire pmu_corec_sleep_in;
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wire smpu_deny;
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wire sys_rst;
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//***********************Instance cpu_sub_system_ahb****************************
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// &Instance("cpu_sub_system_ahb", "x_cpu_sub_system_ahb"); @31
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// &Connect( @32
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// .clk_en (clk_en ) @33
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// ); @34
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// Support AHB_LITE
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// &Instance("cpu_sub_system_ahb", "x_cpu_sub_system_ahb"); @38
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cpu_sub_system_ahb x_cpu_sub_system_ahb (
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.biu_pad_haddr (biu_pad_haddr ),
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.biu_pad_hburst (biu_pad_hburst ),
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.biu_pad_hprot (biu_pad_hprot ),
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.biu_pad_hsize (biu_pad_hsize ),
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.biu_pad_htrans (biu_pad_htrans ),
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.biu_pad_hwdata (biu_pad_hwdata ),
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.biu_pad_hwrite (biu_pad_hwrite ),
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.biu_pad_lpmd_b (biu_pad_lpmd_b ),
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.clk_en (clk_en ),
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.corec_pmu_sleep_out (corec_pmu_sleep_out ),
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.cpu_clk (cpu_clk ),
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.had_pad_jtg_tdo (had_pad_jtg_tdo ),
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.nmi_wake_int_lower (nmi_wake_int_lower ),
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.pad_biu_bigend_b (1'b1 ),
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.pad_biu_hrdata (pad_biu_hrdata ),
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.pad_biu_hready (fifo_biu_hready ),
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.pad_biu_hresp (pad_biu_hresp ),
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.pad_cpu_rst_b (pad_cpu_rst_b ),
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.pad_had_jtg_tclk (pad_had_jtg_tclk ),
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.pad_had_jtg_tdi (pad_had_jtg_tdi ),
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.pad_had_jtg_tms (pad_had_jtg_tms ),
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.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
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.pad_vic_int_vld (pad_vic_int_vld ),
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.pad_yy_icg_scan_en (1'b0 ),
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.pad_yy_scan_enable (1'b0 ),
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.pad_yy_scan_mode (1'b0 ),
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.pad_yy_scan_rst_b (1'b1 ),
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.pg_reset_b (pg_reset_b ),
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.pmu_corec_isolation (pmu_corec_isolation ),
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.pmu_corec_sleep_in (pmu_corec_sleep_in ),
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.sys_rst (sys_rst )
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);
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// &Connect(.clk_en (clk_en ), @40
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// .pad_yy_gate_clk_en_b (1'b0 ), @41
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// .pad_yy_bist_tst_en (1'b0 ), @42
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// .pad_yy_scan_enable (1'b0 ), @43
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// .pad_yy_scan_mode (1'b0 ), @44
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// .pad_yy_icg_scan_en (1'b0 ), @45
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// .pad_yy_scan_rst_b (1'b1 ), @46
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// .pad_yy_dft_clk_rst_b (1'b1 ), @47
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// .pad_biu_bigend_b (1'b1 ), @48
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// .pad_biu_int_b (1'b1 ), @49
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// .pad_biu_fint_b (1'b1 ), @50
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// .pad_biu_fintraw_b (1'b1 ), @51
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// .pad_biu_avec_b (1'b0 ), @52
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// .pad_biu_vec_b (8'b0 ), @53
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// .pad_biu_gsb (32'b0 ), @54
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// //add for debug @55
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// .pad_biu_dbgrq_b (1'b1 ), @56
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// .pad_had_jtg_tap_en (1'b1 ), @57
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// .pad_biu_clkratio (3'b0 ), @58
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// .pad_biu_hready (fifo_biu_hready ) @59
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// ); @60
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assign i_pad_cpu_jtg_rst_b = i_pad_rst_b & i_pad_jtg_trst_b;
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//assign pad_cpu_rst_b = i_pad_rst_b;
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assign pad_cpu_rst_b = i_pad_jtg_nrst_b;
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//assign pll_core_cpuclk = cpu_clk;
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assign pad_had_jtg_tclk = i_pad_jtg_tclk;
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//assign pad_had_jtg_trst_b_pre = i_pad_jtg_trst_b;
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assign pad_had_jtg_trst_b_pre = i_pad_cpu_jtg_rst_b;
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assign o_pad_jtg_tdo = had_pad_jtg_tdo;
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assign pad_had_jtg_tdi = i_pad_jtg_tdi;
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assign pad_had_jtg_tms = i_pad_jtg_tms;
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// //&Force("inout","i_pad_jtg_tms"); @79
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// //&Force("nonport","pad_had_jtg_tms"); @82
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// &Force("nonport","had_pad_jdb_ack_b"); @84
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//***********************Instance ahb delay simulator ***********************
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// &Instance("ahb_fifo", "x_ahb_fifo"); @86
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ahb_fifo x_ahb_fifo (
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.biu_pad_haddr (biu_pad_haddr ),
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.biu_pad_hburst (biu_pad_hburst[1:0]),
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.biu_pad_hprot (biu_pad_hprot ),
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.biu_pad_hsize (biu_pad_hsize ),
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.biu_pad_htrans (biu_pad_htrans ),
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.biu_pad_hwrite (biu_pad_hwrite ),
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.counter_num0 (32'h1 ),
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.cpu_clk (per_clk ),
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.cpu_rst_b (pg_reset_b ),
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.fifo_biu_hready (fifo_biu_hready),
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.fifo_pad_haddr (fifo_pad_haddr ),
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.fifo_pad_hburst (fifo_pad_hburst[1:0]),
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.fifo_pad_hprot (fifo_pad_hprot ),
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.fifo_pad_hsize (fifo_pad_hsize ),
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.fifo_pad_htrans (fifo_pad_htrans),
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.fifo_pad_hwrite (fifo_pad_hwrite),
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.pad_biu_hready (pad_biu_hready )
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);
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// &Connect( @87
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// .cpu_clk (per_clk ), @88
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// .cpu_rst_b (pg_reset_b ), @89
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// .counter_num0 (32'h1 ) @90
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// ); @91
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//***********************Instance ahb bus arbiter****************************
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// &Instance("ahb", "x_ahb"); @94
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ahb x_ahb (
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.biu_pad_haddr (fifo_pad_haddr ),
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.biu_pad_hburst (fifo_pad_hburst),
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.biu_pad_hprot (fifo_pad_hprot ),
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.biu_pad_hsize (fifo_pad_hsize ),
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.biu_pad_htrans (fifo_pad_htrans),
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.biu_pad_hwdata (biu_pad_hwdata ),
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.biu_pad_hwrite (fifo_pad_hwrite),
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.haddr_s1 (haddr_s1 ),
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.haddr_s2 (haddr_s2 ),
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.haddr_s3 (haddr_s3 ),
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.hburst_s1 (hburst_s1 ),
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.hburst_s3 (hburst_s3 ),
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.hmastlock (hmastlock ),
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.hprot_s1 (hprot_s1 ),
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.hprot_s3 (hprot_s3 ),
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.hrdata_s1 (hrdata_s1 ),
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.hrdata_s2 (hrdata_s2 ),
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.hrdata_s3 (hrdata_s3 ),
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.hready_s1 (hready_s1 ),
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.hready_s2 (hready_s2 ),
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.hready_s3 (hready_s3 ),
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.hresp_s1 (hresp_s1 ),
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.hresp_s2 (hresp_s2 ),
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.hresp_s3 (hresp_s3 ),
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.hsel_s1 (hsel_s1 ),
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.hsel_s2 (hsel_s2 ),
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.hsel_s3 (hsel_s3 ),
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.hsize_s1 (hsize_s1 ),
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.hsize_s3 (hsize_s3 ),
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.htrans_s1 (htrans_s1 ),
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.htrans_s3 (htrans_s3 ),
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.hwdata_s1 (hwdata_s1 ),
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.hwdata_s2 (hwdata_s2 ),
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.hwdata_s3 (hwdata_s3 ),
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.hwrite_s1 (hwrite_s1 ),
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.hwrite_s2 (hwrite_s2 ),
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.hwrite_s3 (hwrite_s3 ),
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.pad_biu_hrdata (pad_biu_hrdata ),
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.pad_biu_hready (pad_biu_hready ),
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.pad_biu_hresp (pad_biu_hresp ),
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.pad_cpu_rst_b (pg_reset_b ),
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.pll_core_cpuclk (per_clk ),
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.smpu_deny (smpu_deny )
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);
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// &Connect( @95
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// .pll_core_cpuclk (per_clk ), @96
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// .pad_cpu_rst_b (pg_reset_b ), @97
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// .biu_pad_hbusreq (fifo_pad_hreq ), @98
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// .biu_pad_haddr (fifo_pad_haddr ), @99
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// .biu_pad_hburst (fifo_pad_hburst ), @100
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// .biu_pad_hlock (fifo_pad_hlock ), @101
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// .biu_pad_hprot (fifo_pad_hprot ), @102
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// .biu_pad_hsize (fifo_pad_hsize ), @103
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// .biu_pad_htrans (fifo_pad_htrans ), @104
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// .biu_pad_hwrite (fifo_pad_hwrite ) @105
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// ); @106
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//***********************Instance ahb slave 1 ****************************
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// &Instance("mem_ctrl", "x_smem_ctrl"); @110
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mem_ctrl x_smem_ctrl (
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.haddr_s1 (haddr_s1 ),
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.hburst_s1 (hburst_s1 ),
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.hprot_s1 (hprot_s1 ),
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.hrdata_s1 (hrdata_s1 ),
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.hready_s1 (hready_s1 ),
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.hresp_s1 (hresp_s1 ),
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.hsel_s1 (hsel_s1 ),
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.hsize_s1 (hsize_s1 ),
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|
.htrans_s1 (htrans_s1 ),
|
||
|
|
.hwdata_s1 (hwdata_s1 ),
|
||
|
|
.hwrite_s1 (hwrite_s1 ),
|
||
|
|
.pad_cpu_rst_b (pad_cpu_rst_b ),
|
||
|
|
.pll_core_cpuclk (per_clk )
|
||
|
|
);
|
||
|
|
|
||
|
|
// &Connect( @111
|
||
|
|
// .pll_core_cpuclk (per_clk ) @112
|
||
|
|
// ); @113
|
||
|
|
|
||
|
|
//***********************Instance ahb slave 2 ****************************
|
||
|
|
|
||
|
|
// &Instance("apb", "x_apb"); @117
|
||
|
|
apb x_apb (
|
||
|
|
.b_pad_gpio_porta (b_pad_gpio_porta ),
|
||
|
|
.biu_pad_lpmd_b (biu_pad_lpmd_b ),
|
||
|
|
.clk_en (clk_en ),
|
||
|
|
.corec_pmu_sleep_out (corec_pmu_sleep_out ),
|
||
|
|
.cpu_clk (cpu_clk ),
|
||
|
|
.fifo_pad_haddr (fifo_pad_haddr ),
|
||
|
|
.fifo_pad_hprot (fifo_pad_hprot ),
|
||
|
|
.haddr_s2 (haddr_s2 ),
|
||
|
|
.hrdata_s2 (hrdata_s2 ),
|
||
|
|
.hready_s2 (hready_s2 ),
|
||
|
|
.hresp_s2 (hresp_s2 ),
|
||
|
|
.hsel_s2 (hsel_s2 ),
|
||
|
|
.hwdata_s2 (hwdata_s2 ),
|
||
|
|
.hwrite_s2 (hwrite_s2 ),
|
||
|
|
.i_pad_cpu_jtg_rst_b (i_pad_cpu_jtg_rst_b ),
|
||
|
|
.i_pad_jtg_tclk (i_pad_jtg_tclk ),
|
||
|
|
.nmi_wake_int_lower (nmi_wake_int_lower ),
|
||
|
|
.pad_clk (i_pad_clk ),
|
||
|
|
.pad_cpu_rst_b (pad_cpu_rst_b ),
|
||
|
|
.pad_had_jtg_tap_en (1'b1 ),
|
||
|
|
.pad_had_jtg_tms_i (1'b1 ),
|
||
|
|
.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
|
||
|
|
.pad_had_jtg_trst_b_pre (pad_had_jtg_trst_b_pre),
|
||
|
|
.pad_vic_int_vld (pad_vic_int_vld ),
|
||
|
|
.per_clk (per_clk ),
|
||
|
|
.pg_reset_b (pg_reset_b ),
|
||
|
|
.pmu_corec_isolation (pmu_corec_isolation ),
|
||
|
|
.pmu_corec_sleep_in (pmu_corec_sleep_in ),
|
||
|
|
.smpu_deny (smpu_deny ),
|
||
|
|
.sys_rst (sys_rst ),
|
||
|
|
.uart0_sin (i_pad_uart0_sin ),
|
||
|
|
.uart0_sout (o_pad_uart0_sout )
|
||
|
|
);
|
||
|
|
|
||
|
|
// &Connect(.pad_clk (i_pad_clk ), @118
|
||
|
|
// .uart0_sin (i_pad_uart0_sin ), @119
|
||
|
|
// .uart0_sout (o_pad_uart0_sout ), @120
|
||
|
|
// .gpio_ext_porta (i_pad_gpio_porta ), @121
|
||
|
|
// .gpio_ext_portb (i_pad_gpio_portb ), @122
|
||
|
|
// .gpio_porta_dr (o_pad_gpio_porta ), @123
|
||
|
|
// .gpio_portb_dr (o_pad_gpio_portb ), @124
|
||
|
|
// .gpio_portb_dr (o_pad_gpio_portb ), @125
|
||
|
|
// .pad_had_jtg_tms_i (1'b1 ), @126
|
||
|
|
// .pad_had_jtg_tap_en (1'b1 ) @127
|
||
|
|
// @128
|
||
|
|
// @129
|
||
|
|
// ); @130
|
||
|
|
//***********************Instance ahb slave 3 ****************************
|
||
|
|
|
||
|
|
// &Instance("err_gen", "x_err_gen"); @133
|
||
|
|
err_gen x_err_gen (
|
||
|
|
.haddr_s3 (haddr_s3 ),
|
||
|
|
.hburst_s3 (hburst_s3 ),
|
||
|
|
.hmastlock (hmastlock ),
|
||
|
|
.hprot_s3 (hprot_s3 ),
|
||
|
|
.hrdata_s3 (hrdata_s3 ),
|
||
|
|
.hready_s3 (hready_s3 ),
|
||
|
|
.hresp_s3 (hresp_s3 ),
|
||
|
|
.hsel_s3 (hsel_s3 ),
|
||
|
|
.hsize_s3 (hsize_s3 ),
|
||
|
|
.htrans_s3 (htrans_s3 ),
|
||
|
|
.hwdata_s3 (hwdata_s3 ),
|
||
|
|
.hwrite_s3 (hwrite_s3 ),
|
||
|
|
.pad_cpu_rst_b (pg_reset_b ),
|
||
|
|
.pll_core_cpuclk (per_clk )
|
||
|
|
);
|
||
|
|
|
||
|
|
// &Connect ( @134
|
||
|
|
// .pll_core_cpuclk (per_clk ), @135
|
||
|
|
// .pad_cpu_rst_b (pg_reset_b ) @136
|
||
|
|
// ); @137
|
||
|
|
|
||
|
|
//***********************Instance ahb slave 4 ****************************
|
||
|
|
// &Instance("mem_ctrl", "x_imem_ctrl"); @142
|
||
|
|
// &Connect( @143
|
||
|
|
// .haddr_s1 (haddr_s4 ), @144
|
||
|
|
// .hburst_s1 (hburst_s4 ), @145
|
||
|
|
// .hprot_s1 (hprot_s4 ), @146
|
||
|
|
// .hrdata_s1 (hrdata_s4 ), @147
|
||
|
|
// .hready_s1 (hready_s4 ), @148
|
||
|
|
// .hresp_s1 (hresp_s4 ), @149
|
||
|
|
// .hsel_s1 (hsel_s4 ), @150
|
||
|
|
// .hsize_s1 (hsize_s4 ), @151
|
||
|
|
// .htrans_s1 (htrans_s4 ), @152
|
||
|
|
// .hwdata_s1 (hwdata_s4 ), @153
|
||
|
|
// .hwrite_s1 (hwrite_s4 ), @154
|
||
|
|
// .pll_core_cpuclk (per_clk ) @155
|
||
|
|
// ); @156
|
||
|
|
|
||
|
|
//***********************Instance ahb slave 5 ****************************
|
||
|
|
// &Instance("mem_ctrl", "x_dmem_ctrl"); @162
|
||
|
|
// &Connect( @163
|
||
|
|
// .haddr_s1 (haddr_s5 ), @164
|
||
|
|
// .hburst_s1 (hburst_s5 ), @165
|
||
|
|
// .hprot_s1 (hprot_s5 ), @166
|
||
|
|
// .hrdata_s1 (hrdata_s5 ), @167
|
||
|
|
// .hready_s1 (hready_s5 ), @168
|
||
|
|
// .hresp_s1 (hresp_s5 ), @169
|
||
|
|
// .hsel_s1 (hsel_s5 ), @170
|
||
|
|
// .hsize_s1 (hsize_s5 ), @171
|
||
|
|
// .htrans_s1 (htrans_s5 ), @172
|
||
|
|
// .hwdata_s1 (hwdata_s5 ), @173
|
||
|
|
// .hwrite_s1 (hwrite_s5 ), @174
|
||
|
|
// .pll_core_cpuclk (per_clk ) @175
|
||
|
|
// ); @176
|
||
|
|
|
||
|
|
// &Force("nonport","pad_dahbl_hsec"); @179
|
||
|
|
// &Force("nonport","pad_iahbl_hsec"); @180
|
||
|
|
// &ModuleEnd; @181
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|