102 lines
2.5 KiB
Coq
102 lines
2.5 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module err_gen(
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haddr_s3,
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hburst_s3,
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hmastlock,
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hprot_s3,
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hrdata_s3,
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hready_s3,
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hresp_s3,
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hsel_s3,
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hsize_s3,
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htrans_s3,
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hwdata_s3,
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hwrite_s3,
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pad_cpu_rst_b,
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pll_core_cpuclk
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);
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// &Ports; @23
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input [31:0] haddr_s3;
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input [2 :0] hburst_s3;
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input hmastlock;
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input [3 :0] hprot_s3;
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input hsel_s3;
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input [2 :0] hsize_s3;
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input [1 :0] htrans_s3;
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input [31:0] hwdata_s3;
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input hwrite_s3;
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input pad_cpu_rst_b;
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input pll_core_cpuclk;
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output [31:0] hrdata_s3;
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output hready_s3;
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output [1 :0] hresp_s3;
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// &Regs; @24
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reg hready_s3;
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// &Wires; @25
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wire [31:0] hrdata_s3;
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wire [1 :0] hresp_s3;
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wire hsel_s3;
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wire pad_cpu_rst_b;
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wire pll_core_cpuclk;
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// //&Force("input","pll_core_cpuclk"); @26
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// //&Force("input","pad_cpu_rst_b"); @27
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// &Force("input","hsel_s3"); @28
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// &Force("input","haddr_s3"); @29
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// &Force("bus", "haddr_s3", 31,0); @30
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// &Force("input","hburst_s3"); @31
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// &Force("bus", "hburst_s3", 2,0); @32
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// &Force("input","hmastlock"); @33
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// &Force("input","hprot_s3"); @34
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// &Force("bus", "hprot_s3", 3,0); @35
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// &Force("input","hsize_s3"); @36
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// &Force("bus", "hsize_s3", 2,0); @37
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// &Force("input","htrans_s3"); @38
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// &Force("bus", "htrans_s3", 1,0); @39
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// &Force("input","hwdata_s3"); @40
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// &Force("input","hwrite_s3"); @41
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// &Force("input","hsel_s3"); @42
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// &Force("output","hready_s3"); @43
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//assign hready_s3 = 1'b1;
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assign hresp_s3[1:0] = 2'b01 ;
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always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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begin
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hready_s3 <= 1'b0;
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end
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else if(hsel_s3)
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begin
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hready_s3 <= 1'b0;
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end
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else
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begin
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hready_s3 <= 1'b1;
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end
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end
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// &Force("bus", "hwdata_s3", 31,0); @63
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assign hrdata_s3[31:0] = 32'b0;
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// &ModuleEnd; @66
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endmodule
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