abstractaccelerator/Cores-SweRV/tools/Makefile

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# SPDX-License-Identifier: Apache-2.0
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# Copyright 2020 Western Digital Corporation or its affiliates.
#
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# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
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CONF_PARAMS = -set iccm_enable
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# Check for RV_ROOT
ifeq (,$(wildcard ${RV_ROOT}/configs/swerv.config))
$(error env var RV_ROOT does not point to a valid dir! Exiting!)
endif
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TEST_CFLAGS = -g -O3 -funroll-all-loops
ABI = -mabi=ilp32 -march=rv32imc
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# Allow snapshot override
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target = default
snapshot = $(target)
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# Allow tool override
SWERV_CONFIG = ${RV_ROOT}/configs/swerv.config
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IRUN = xrun
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VCS = vcs
VERILATOR = verilator
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VLOG = qverilog
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RIVIERA = riviera
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GCC_PREFIX = riscv64-unknown-elf
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BUILD_DIR = snapshots/${snapshot}
TBDIR = ${RV_ROOT}/testbench
# Define default test name
TEST = hello_world
# Define default test directory
TEST_DIR = $(TBDIR)/asm
HEX_DIR = $(TBDIR)/hex
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ifneq (,$(wildcard $(TBDIR)/tests/$(TEST)))
TEST_DIR = $(TBDIR)/tests/$(TEST)
endif
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ifdef debug
DEBUG_PLUS = +dumpon
IRUN_DEBUG = -access +rc
IRUN_DEBUG_RUN = -input ${RV_ROOT}/testbench/input.tcl
VCS_DEBUG = -debug_access
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VERILATOR_DEBUG = --trace
RIVIERA_DEBUG = +access +r
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endif
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# provide specific link file
ifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))
LINK = $(TBDIR)/link.ld
else
LINK = $(TEST_DIR)/$(TEST).ld
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endif
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OFILES = $(TEST).o
-include $(TEST_DIR)/$(TEST).mki
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VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
TBFILES = $(TBDIR)/tb_top.sv $(TBDIR)/ahb_sif.sv
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defines = $(BUILD_DIR)/common_defines.vh ${RV_ROOT}/design/include/swerv_types.sv
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includes = -I${RV_ROOT}/design/include -I${RV_ROOT}/design/lib -I${BUILD_DIR}
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
# -O2 for faster runtime (slower compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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# Targets
all: clean verilator
clean:
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rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots swerv* \
verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv \
work dataset.asdb library.cfg
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# If define files do not exist, then run swerv.config.
${BUILD_DIR}/defines.h :
BUILD_PATH=${BUILD_DIR} ${SWERV_CONFIG} -target=$(target) $(CONF_PARAMS)
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##################### Verilog Builds #####################################
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verilator-build: ${TBFILES} ${BUILD_DIR}/defines.h test_tb_top.cpp
echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
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-Wno-UNOPTFLAT \
-I${RV_ROOT}/testbench \
-f ${RV_ROOT}/testbench/flist \
${TBFILES} \
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--top-module tb_top -exe test_tb_top.cpp --autoflush $(VERILATOR_DEBUG)
cp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
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touch verilator-build
vcs-build: ${TBFILES} ${BUILD_DIR}/defines.h
$(VCS) -full64 -assert svaext -sverilog +error+500 \
+incdir+${RV_ROOT}/design/lib \
+incdir+${RV_ROOT}/design/include \
+incdir+${BUILD_DIR} +libext+.v\
$(defines) -f ${RV_ROOT}/testbench/flist\
${TBFILES} \
-l vcs_compile.log
touch vcs-build
irun-build: ${TBFILES} ${BUILD_DIR}/defines.h
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$(IRUN) -64bit -elaborate $(IRUN_DEBUG) -q -sv -sysv -nowarn CUVIHR -xmlibdirpath . -xmlibdirname swerv.build \
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-incdir ${RV_ROOT}/design/lib -incdir ${RV_ROOT}/design/include -incdir ${BUILD_DIR} -vlog_ext +.vh+.h\
$(defines) -f ${RV_ROOT}/testbench/flist\
-top tb_top ${TBFILES} -I${RV_ROOT}/testbench \
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-elaborate -snapshot $(snapshot) $(profile)
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touch irun-build
riviera-build: ${TBFILES} ${BUILD_DIR}/defines.h
vlib work
vlog -work work \
+incdir+${RV_ROOT}/design/lib \
+incdir+${RV_ROOT}/design/include \
+incdir+${BUILD_DIR} +libext+.v $(defines) \
-f ${RV_ROOT}/testbench/flist \
${TBFILES}
touch riviera-build
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##################### Simulation Runs #####################################
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verilator: program.hex verilator-build
./obj_dir/Vtb_top ${DEBUG_PLUS}
irun: program.hex irun-build
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$(IRUN) -64bit +lic_queue -licqueue -status -xmlibdirpath . -xmlibdirname swerv.build \
-snapshot ${snapshot} -r ${snapshot} $(IRUN_DEBUG_RUN) $(profile)
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vcs: program.hex vcs-build
./simv $(DEBUG_PLUS) +vcs+lic+wait -l vcs.log
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vlog: program.hex ${TBFILES} ${BUILD_DIR}/defines.h
$(VLOG) -l vlog.log -sv -mfcu +incdir+${BUILD_DIR}+${RV_ROOT}/design/include+${RV_ROOT}/design/lib\
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$(defines) -f ${RV_ROOT}/testbench/flist ${TBFILES} -R +nowarn3829 ${DEBUG_PLUS}
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riviera: program.hex riviera-build
vsim -c -lib work ${DEBUG_PLUS} ${RIVIERA_DEBUG} tb_top -do "run -all; exit" -l riviera.log
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##################### Test Build #####################################
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ifeq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)
program.hex: ${BUILD_DIR}/defines.h
@echo " !!! No $(GCC_PREFIX)-gcc in path, using canned hex files !!"
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cp ${HEX_DIR}/$(TEST).hex program.hex
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else
ifneq (,$(wildcard $(TEST_DIR)/$(TEST).makefile))
program.hex:
$(MAKE) -f $(TEST_DIR)/$(TEST).makefile
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else
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program.hex: $(OFILES) $(LINK)
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@echo Building $(TEST)
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$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TEST).map -lgcc -T$(LINK) -o $(TEST).exe $(OFILES) -nostartfiles $(TEST_LIBS)
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$(GCC_PREFIX)-objcopy -O verilog $(TEST).exe program.hex
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$(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis
@echo Completed building $(TEST)
%.o : %.s ${BUILD_DIR}/defines.h
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$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $*.cpp.s
$(GCC_PREFIX)-as $(ABI) $*.cpp.s -o $@
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%.o : %.c ${BUILD_DIR}/defines.h
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$(GCC_PREFIX)-gcc -I${BUILD_DIR} ${TEST_CFLAGS} ${ABI} -nostdlib -c $< -o $@
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endif
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endif
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help:
@echo Make sure the environment variable RV_ROOT is set.
@echo Possible targets: verilator vcs irun vlog riviera help clean all verilator-build irun-build vcs-build riviera-build program.hex
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.PHONY: help clean verilator vcs irun vlog riviera