104 lines
2.3 KiB
Coq
104 lines
2.3 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @19
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module fpga_clk_gen(
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clk_en,
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clkrst_b,
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cpu_clk,
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gate_en0,
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gate_en1,
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pad_clk,
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penable,
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per_clk,
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pmu_clk,
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prdata,
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psel,
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pwdata,
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pwrite,
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wic_clk
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);
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// &Ports; @20
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input clkrst_b;
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input gate_en0;
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input gate_en1;
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input pad_clk;
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input penable;
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input psel;
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input [2 :0] pwdata;
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input pwrite;
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output clk_en;
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output cpu_clk;
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output per_clk;
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output pmu_clk;
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output [31:0] prdata;
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output wic_clk;
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// &Regs; @21
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reg [2 :0] input_clkratio;
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reg [31:0] prdata;
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// &Wires; @22
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wire clk_en;
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wire clkrst_b;
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wire cpu_clk;
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wire pad_clk;
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wire penable;
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wire per_clk;
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wire pmu_clk;
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wire psel;
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wire [2 :0] pwdata;
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wire pwrite;
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wire wic_clk;
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always@(posedge per_clk or negedge clkrst_b)
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begin
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if (!clkrst_b)
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input_clkratio[2:0] <= 3'b0;
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else if(psel && pwrite && penable)
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input_clkratio[2:0] <= pwdata[2:0];
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end
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// &CombBeg; @32
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always @( psel
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or pwrite)
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begin
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if(psel && !pwrite)
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begin
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prdata[31:0] <= 32'b0;
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end
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// &CombEnd; @37
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end
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assign cpu_clk = pad_clk;
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assign wic_clk = pad_clk;
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assign per_clk = pad_clk;
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assign pmu_clk = pad_clk;
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assign clk_en = 1'b1;
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// &Force("output","per_clk"); @45
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// &Force("input", "gate_en0"); @48
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// &Force("input", "gate_en1"); @49
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// &Force("nonport", "input_clkratio"); @50
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// &ModuleEnd; @52
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endmodule
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