447 lines
11 KiB
Coq
447 lines
11 KiB
Coq
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`define E906
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`define SOC_TOP tb.x_soc
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`define RTL_MEM tb.x_soc.x_smem_ctrl
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`define ISA_MEM tb.x_pa_isa
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`define JTAG_5
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`define IAHB_LITE
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`ifdef IAHB_LITE
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`define RTL_IAHBL_MEM tb.x_soc.x_cpu_sub_system_ahb.x_iahb_mem_ctrl
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`else
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`define RTL_IAHBL_MEM tb.x_soc.x_imem_ctrl
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`endif
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`define DAHB_LITE
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`ifdef DAHB_LITE
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`define RTL_DAHBL_MEM tb.x_soc.x_cpu_sub_system_ahb.x_dahb_mem_ctrl
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`else
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`define RTL_DAHBL_MEM tb.x_soc.x_dmem_ctrl
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`endif
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//clock period
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`define CLK_PERIOD 10
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`define TCLK_PERIOD 33
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`define MAX_RUN_TIME 700000000
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`define clk tb.clk
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`define rst_b tb.rst_b
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// `include "../cpu/environment.h"
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`timescale 1ns/100ps
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module tb();
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reg clk;
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reg jclk;
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reg rst_b;
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reg jrst_b;
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reg nrst_b;
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reg jtap_en;
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//wire jtag2_sel;
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wire jtg_tms;
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wire jtg_tdi;
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wire jtg_tdo;
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wire uart0_sin;
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wire [7:0]b_pad_gpio_porta;
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static integer FILE;
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//Clock Generator
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initial
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begin
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clk =0;
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forever begin
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#(`CLK_PERIOD/2) clk = ~clk;
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end
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end
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initial
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begin
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jclk = 0;
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forever begin
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#(`TCLK_PERIOD/2) jclk = ~jclk;
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end
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end
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//Reset Generater
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initial
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begin
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rst_b = 1;
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#100;
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rst_b = 0;
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#100;
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rst_b = 1;
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end
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initial
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begin
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jrst_b = 1;
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#100;
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jrst_b = 0;
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#100;
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jrst_b = 1;
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end
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initial
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begin
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nrst_b = 1;
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#100;
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nrst_b = 0;
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#100;
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nrst_b = 1;
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end
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///////////////////////////////////////
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// Memory Initialization
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///////////////////////////////////////
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integer i;
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reg [31:0] mem_data_size;
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reg [31:0] mem_inst_size;
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reg [31:0] mem_inst_temp [65536];
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reg [31:0] mem_data_temp [65536];
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initial
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begin
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$display("\t******START TO LOAD PROGRAM******\n");
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$readmemh("./case.pat", mem_inst_temp);
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$readmemh("./data.pat", mem_data_temp);
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for(i=0;i<65536;i=i+1)
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begin
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`RTL_IAHBL_MEM.ram0.mem[i][7:0] = ((^mem_inst_temp[i][31:24]) === 1'bx ) ? 8'b0:mem_inst_temp[i][31:24];
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`RTL_IAHBL_MEM.ram1.mem[i][7:0] = ((^mem_inst_temp[i][23:16]) === 1'bx ) ? 8'b0:mem_inst_temp[i][23:16];
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`RTL_IAHBL_MEM.ram2.mem[i][7:0] = ((^mem_inst_temp[i][15: 8]) === 1'bx ) ? 8'b0:mem_inst_temp[i][15: 8];
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`RTL_IAHBL_MEM.ram3.mem[i][7:0] = ((^mem_inst_temp[i][ 7: 0]) === 1'bx ) ? 8'b0:mem_inst_temp[i][ 7: 0];
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end
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for(i=0;i<=65536;i=i+1)
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begin
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`RTL_DAHBL_MEM.ram0.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram1.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram2.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram3.mem[i][7:0] = 8'b0;
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end
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for(i=0;i<=65536;i=i+1)
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begin
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`RTL_DAHBL_MEM.ram4.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram5.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram6.mem[i][7:0] = 8'b0;
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`RTL_DAHBL_MEM.ram7.mem[i][7:0] = 8'b0;
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end
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end
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///////////////////////////////////////
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// Finish Condition Control
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///////////////////////////////////////
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// Reaching the max simulation time.
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reg [31:0] ins_counter;
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initial
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begin
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#`MAX_RUN_TIME;
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$display("**********************************************");
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$display("* meeting max simulation time, stop! *");
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$display("**********************************************");
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FILE = $fopen("run_case.report","w");
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$fdisplay(FILE,"TEST FAIL");
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$finish;
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end
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// No instrunction retired in the last `LAST_CYCLE cycles
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reg [31:0] retire_inst_in_period;
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reg [31:0] cycle_count;
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`define LAST_CYCLE 5000
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always @(posedge clk or negedge rst_b)
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begin
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if(!rst_b)
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cycle_count[31:0] <= 32'b1;
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else
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cycle_count[31:0] <= cycle_count[31:0] + 1'b1;
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end
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always @(posedge clk or negedge rst_b)
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begin
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if(!rst_b) //reset to zero
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retire_inst_in_period[31:0] <= 32'b0;
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else if( (cycle_count[31:0] % `LAST_CYCLE) == 0)//check and reset retire_inst_in_period every 50000 cycles
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begin
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if(retire_inst_in_period[31:0] == 0)begin
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$display("*************************************************************");
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$display("* Error: There is no instructions retired in the last %d cycles! *", `LAST_CYCLE);
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$display("* Simulation Fail and Finished! *");
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$display("*************************************************************");
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#10;
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FILE = $fopen("run_case.report","w");
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$fdisplay(FILE,"TEST FAIL");
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$finish;
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end
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retire_inst_in_period[31:0] <= 32'b0;
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end
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else if(tb.x_soc.x_cpu_sub_system_ahb.biu_pad_retire)
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retire_inst_in_period[31:0] <= retire_inst_in_period[31:0] + 1'b1;
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end
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//Finish control with address 32'h0
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reg [31:0] cpu_addr;
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reg [1:0] cpu_trans;
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reg cpu_write;
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wire [31:0] cpu_wdata;
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always @(posedge clk)
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begin
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cpu_trans[1:0] <= `SOC_TOP.biu_pad_htrans[1:0];
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cpu_addr[31:0] <= `SOC_TOP.biu_pad_haddr[31:0];
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cpu_write <= `SOC_TOP.biu_pad_hwrite;
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end
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assign cpu_wdata[31:0] = `SOC_TOP.biu_pad_hwdata[31:0];
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always @(posedge clk)
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begin
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if((cpu_trans[1:0] == 2'b10) &&
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(cpu_addr[31:0] == 32'h6000fff8) &&
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cpu_write &&
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(cpu_wdata[31:0] == 12'hfff || cpu_wdata[31:0] == 32'hffff0000))
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begin
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$display("\n**********************************************");
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$display("* simulation finished successfully *");
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$display("**********************************************");
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#10;
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FILE = $fopen("run_case.report","w");
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$fdisplay(FILE,"TEST PASS");
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$finish;
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end
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else if((cpu_trans[1:0] == 2'b10) &&
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(cpu_addr[31:0] == 32'h6000fff8) &&
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cpu_write &&
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(cpu_wdata[31:0] == 12'heee || cpu_wdata[31:0] == 32'heeee0000))
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begin
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$display("**********************************************");
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$display("* simulation finished with error *");
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$display("**********************************************");
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#10;
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FILE = $fopen("run_case.report","w");
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$fdisplay(FILE,"TEST FAIL");
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$finish;
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end
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else if((cpu_trans[1:0] == 2'b10) &&
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(cpu_addr[31:0] == 32'h6000fff8) &&
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cpu_write)
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begin
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// $write("begin to display:");
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$write("%c", cpu_wdata[7:0]);
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end
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end
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//Dumping Control
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`ifndef NO_DUMP
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initial
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begin
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`ifdef NC_SIM
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$dumpfile("test.vcd");
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$dumpvars;
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`else
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`ifdef IVERILOG_SIM
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$dumpfile("test.vcd");
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$dumpvars;
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`else
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$fsdbDumpvars();
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`endif
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`endif
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end
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`endif
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//Monitor
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`ifndef NO_MONITOR
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mnt x_mnt();
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`endif
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uart_mnt x_uart_mnt();
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assign jtg_tdi = 1'b0;
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assign uart0_sin = 1'b1;
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//instantiate soc
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soc x_soc(
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.i_pad_clk ( clk ),
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.i_pad_uart0_sin ( uart0_sin ),
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.o_pad_uart0_sout ( uart0_sout ),
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.i_pad_jtg_tclk ( jclk ),
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.i_pad_jtg_trst_b ( jrst_b ),
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.i_pad_jtg_nrst_b ( nrst_b ),
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.b_pad_gpio_porta ( b_pad_gpio_porta ),
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`ifdef JTAG_5
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.i_pad_jtg_tdi ( jtg_tdi ),
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.o_pad_jtg_tdo ( jtg_tdo ),
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`endif
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.i_pad_jtg_tms ( jtg_tms ),
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`ifdef RST_ACTIVE_HIGH
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.i_pad_rst ( !rst_b )
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`else
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.i_pad_rst_b ( rst_b )
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`endif
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);
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`ifdef PG_SIM
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`define MAX_ARCH_STRLEN 100
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function supply_on;
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//input string pad_name;
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input [8*`MAX_ARCH_STRLEN : 1] pad_name;
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input real value;
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begin
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supply_on = $mvsim_supply_on(pad_name, value);
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end
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endfunction
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function supply_off;
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//input string pad_name;
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input [8*`MAX_ARCH_STRLEN : 1] pad_name;
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begin
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supply_off = $mvsim_supply_off(pad_name);
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end
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endfunction
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real sp_on_vdd;
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real sp_on_vss;
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initial
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begin
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sp_on_vdd = supply_on("VDD", 1.2);
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sp_on_vss = supply_on("VSS", 0);
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// #1000
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// force tb.x_soc.pad_cpu_rst_b = 1'b0;
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// #20
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// force tb.x_soc.x_cpu_sub_system_ahb.x_ck803s.pmu_corec_isolation = 1'b1;
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// #20
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// force tb.x_soc.x_cpu_sub_system_ahb.x_ck803s.pmu_corec_sleep_in = 1'b1;
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//
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// #500
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//
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// release tb.x_soc.x_cpu_sub_system_ahb.x_ck803s.pmu_corec_sleep_in ;
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// #20
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// release tb.x_soc.x_cpu_sub_system_ahb.x_ck803s.pmu_corec_isolation;
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// #20
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// release tb.x_soc.pad_cpu_rst_b ;
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end
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initial
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begin
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$deposit(tb.x_soc.x_cpu_sub_system_ahb.pmu_corec_sleep_in, 1'b0);
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$deposit(tb.x_soc.x_cpu_sub_system_ahb.pmu_corec_isolation, 1'b0);
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$deposit(tb.x_soc.x_cpu_sub_system_ahb.corec_pmu_sleep_out, 1'b0);
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end
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`endif
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`ifdef E902
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`define CPU_TOP tb.x_soc.x_cpu_sub_system_ahb.x_e902
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`elsif E906
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`define CPU_TOP tb.x_soc.x_cpu_sub_system_ahb.x_e906_top
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`else
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`define CPU_TOP tb.x_soc.x_cpu_sub_system_ahb.x_ck803s
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`endif
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`define CPU_CLK `CPU_TOP.pll_core_cpuclk
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`define CPU_RST `CPU_TOP.pad_cpu_rst_b
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||
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`ifdef E902
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||
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`define VIRTUAL_READ `CPU_TOP.x_cr_tcipif_top.x_cr_tcipif_dbus.dummy_addr_cmplt
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||
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`elsif E906
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||
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`define VIRTUAL_READ `CPU_TOP.x_pa_tcipif_top.x_pa_tcipif_dbus.dummy_addr_cmplt
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||
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`else
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||
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`define VIRTUAL_READ `CPU_TOP.x_vg_tcip_top.x_nm_tcipif_dbus.dummy_addr_cmplt
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||
|
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`endif
|
||
|
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`ifdef E902
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||
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`define VIRTUAL_TIME `CPU_TOP.x_cr_tcipif_top.x_cr_tcipif_dbus.tcipif_rd_data[31:0]
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||
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`elsif E906
|
||
|
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`define VIRTUAL_TIME `CPU_TOP.x_pa_tcipif_top.x_pa_tcipif_dbus.tcipif_bmu_dbus_data[31:0]
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||
|
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`else
|
||
|
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`define VIRTUAL_TIME `CPU_TOP.x_vg_tcip_top.x_nm_tcipif_dbus.tcipif_dbus_rd_data[31:0]
|
||
|
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`endif
|
||
|
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|
||
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reg [31:0] virtual_counter;
|
||
|
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|
||
|
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always @(posedge `CPU_CLK or negedge `CPU_RST)
|
||
|
|
begin
|
||
|
|
if(!`CPU_RST)
|
||
|
|
virtual_counter[31:0] <= 32'b0;
|
||
|
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else if(virtual_counter[31:0]==32'hffffffff)
|
||
|
|
virtual_counter[31:0] <= virtual_counter[31:0];
|
||
|
|
else
|
||
|
|
virtual_counter[31:0] <= virtual_counter[31:0] +1'b1;
|
||
|
|
end
|
||
|
|
|
||
|
|
initial
|
||
|
|
begin
|
||
|
|
#1;
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
#1;
|
||
|
|
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
#1;
|
||
|
|
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
#1;
|
||
|
|
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
|
||
|
|
#1;
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
|
||
|
|
#1;
|
||
|
|
wait (`VIRTUAL_READ==1'b1);
|
||
|
|
force `VIRTUAL_TIME = virtual_counter[31:0];
|
||
|
|
@(posedge `CPU_CLK);
|
||
|
|
release `VIRTUAL_TIME;
|
||
|
|
#1;
|
||
|
|
end
|
||
|
|
|
||
|
|
// count instruction number
|
||
|
|
always @(posedge `CPU_CLK or negedge `CPU_RST)
|
||
|
|
begin
|
||
|
|
if(!`CPU_RST)
|
||
|
|
ins_counter[31:0] <= 32'b0;
|
||
|
|
else if(`SOC_TOP.x_cpu_sub_system_ahb.biu_pad_retire &&
|
||
|
|
(`SOC_TOP.x_cpu_sub_system_ahb.biu_pad_retire_pc[31:0] > 32'had4))
|
||
|
|
ins_counter[31:0] <= ins_counter[31:0] + 1'b1;
|
||
|
|
else
|
||
|
|
ins_counter[31:0] <= ins_counter[31:0];
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|